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  1. 25 May, 2021 1 commit
    • Jeremy Linton's avatar
      rpi4: update the iobase constant · 2973dc5d
      Jeremy Linton authored 
      

The PCIe root port is outside of the current RPi
MMIO regions, so we need to adjust the address map.
Given much of the code depends on the legacy IOBASE
lets separate that from the actual MMIO begin/end.
Signed-off-by: default avatarJeremy Linton <jeremy.linton@arm.com>
Change-Id: Id65460ae58556bd8826dba08bbad79953e2a7c0b
      2973dc5d
  3. 19 May, 2021 1 commit
    • Manish V Badarkhe's avatar
      feat(hw_crc): add support for HW computed CRC · a1cedadf
      Manish V Badarkhe authored 
      

Added support for HW computed CRC using Arm ACLE intrinsics.
These are built-in intrinsics available for ARMv8.1-A, and
onwards.
These intrinsics are enabled via '-march=armv8-a+crc' compile
switch for ARMv8-A (supports CRC instructions optionally).

HW CRC support is enabled unconditionally in BL2 for all Arm
platforms.

HW CRC calculation is verified offline to ensure a similar
result as its respective ZLib utility function.

HW CRC calculation support will be used in the upcoming
firmware update patches.

Change-Id: Ia2ae801f62d2003e89a9c3e6d77469b5312614b3
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      a1cedadf
  5. 17 May, 2021 1 commit
  7. 30 Apr, 2021 2 commits
  9. 29 Apr, 2021 2 commits
  11. 28 Apr, 2021 2 commits
    • David Horstmann's avatar
      refactor(plat/arm): store UUID as a string, rather than ints · 7d111d99
      David Horstmann authored 
      

NOTE: Breaking change to the way UUIDs are stored in the DT

Currently, UUIDs are stored in the device tree as
sequences of 4 integers. There is a mismatch in endianness
between the way UUIDs are represented in memory and the way
they are parsed from the device tree. As a result, we must either
store the UUIDs in little-endian format in the DT (which means
that they do not match up with their string representations)
or perform endianness conversion after parsing them.

Currently, TF-A chooses the second option, with unwieldy
endianness-conversion taking place after reading a UUID.

To fix this problem, and to make it convenient to copy and
paste UUIDs from other tools, change to store UUIDs in string
format, using a new wrapper function to parse them from the
device tree.

Change-Id: I38bd63c907be14e412f03ef0aab9dcabfba0eaa0
Signed-off-by: default avatarDavid Horstmann <david.horstmann@arm.com>
      7d111d99
    • Manish V Badarkhe's avatar
      refactor(plat/arm): replace FIP base and size macro with a generic name · 49e9ac28
      Manish V Badarkhe authored 
      

Replaced PLAT_ARM_FIP_BASE and PLAT_ARM_FIP_MAX_SIZE macro with a
generic name PLAT_ARM_FLASH_IMAGE_BASE and PLAT_ARM_FLASH_IMAGE_MAX_SIZE
so that these macros can be reused in the subsequent GPT based support
changes.

Change-Id: I88fdbd53e1966578af4f1e8e9d5fef42c27b1173
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      49e9ac28
  13. 27 Apr, 2021 3 commits
    • Pali Rohár's avatar
      plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC · f2800a47
      Pali Rohár authored 
      

This new compile option is only for Armada 3720 Development Board. When
it is set to 1 then TF-A will setup PM wake up src configuration.

By default this new option is disabled as it is board specific and no
other A37xx board has PM wake up src configuration.

Currently neither upstream U-Boot nor upstream Linux kernel has wakeup
support for A37xx platforms, so having it disabled does not cause any
issue.

Prior this commit PM wake up src configuration specific for Armada 3720
Development Board was enabled for every A37xx board. After this change it
is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766
      f2800a47
    • Aditya Angadi's avatar
      feat(board/rdn2): add support for variant 1 of rd-n2 platform · fe5d5bbf
      Aditya Angadi authored 
      

Add board support for RD-N2 Cfg1 variant of RD-N2 platform. It is a
variant of RD-N2 platform with a reduced interconnect mesh size (3x3)
and core count (8-cores). Its platform variant id is 1.

Change-Id: I34ad35c5a5c1e9b69a658fb92ed00e5bc5fe72f3
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      fe5d5bbf
    • Aditya Angadi's avatar
      feat(plat/sgi): introduce platform variant build option · cfe1506e
      Aditya Angadi authored 
      

A Neoverse reference design platform can have two or more variants that
differ in core count, cluster count or other peripherals. To allow reuse
of platform code across all the variants of a platform, introduce build
option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design
platforms. The range of allowed values for the build option is platform
specific. The recommended range is an interval of non negative integers.

An example usage of the build option is
make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1

Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      cfe1506e
  15. 26 Apr, 2021 1 commit
  17. 23 Apr, 2021 15 commits
  19. 22 Apr, 2021 2 commits
  21. 21 Apr, 2021 5 commits
  23. 20 Apr, 2021 5 commits