GitLab

Main fixes:

* Include header file for function declarations [Rule 8.4]
* Move global object into function [Rule 8.9]

Change-Id: I1bc9f3f0ebd4ffc0b8444ac856cd97b0cb56bda4
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Main fixes:

* Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6]
* Added explicit casts (e.g. 0U) to integers in order for them to be
  compatible with whatever operation they're used in [Rule 10.1]
* Force operands of an operator to the same type category [Rule 10.4]
* Fixed assert/if statements conditions to be essentially boolean [Rule 14.4]
* Added curly braces ({}) around if statements in order to
  make them compound [Rule 15.6]
* Convert macros form headers to unsigned ints

Change-Id: I8051cc16499cece2039c9751bd347645f40f0901
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Main fixes:

* Added explicit casts (e.g. 0U) to integers in order for them to be
  compatible with whatever operation they're used in [Rule 10.1]

* Convert object type to match the type of function parameters
  [Rule 10.3]

* Added curly braces ({}) around if statements in order to
  make them compound [Rule 15.6]

* Expressions resulting from the expansion of macro parameters
  shall be enclosed in parentheses[Rule 20.7]

Change-Id: I5cf83caafcc1650b545ca731bf3eb8f0bfeb362b
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Main fixes:

* Fixed if/while statement conditional to be essentially boolean [Rule 14.4]

* Added curly braces ({}) around if/for/while statements in order to
  make them compound [Rule 15.6]

* Added explicit casts (e.g. 0U) to integers in order for them to be
  compatible with whatever operation they're used in [Rule 10.1]

Change-Id: Ic72b248aeede6cf18bf85051188ea7b8fd8ae829
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

This patch moves the GPU reset state check, during VideoMem resize, to the
common SiP handler, to reduce code duplication.

Change-Id: I3818c5f104b809da83dc2a61d6a8149606f81c13
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch fixes the logic to check if the command written to the
MC_CLIENT_HOTRESET_CTRLx registers, was accepted by the hardware module.

Change-Id: If94fff9424555cb4688042eda17b4b20f4eb399a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds explicit casts (U(x)) to integers in the tegra_def.h
headers, to make them compatible with whatever operation they're used
in [MISRA-C Rule 10.1]

Change-Id: Ic5fc611aad986a2c6e6e6f625e0753ab9b69eb02
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.

NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch enables the 'sign-compare' flag, to enable warning/errors
for comparisons between signed/unsigned variables. The warning has
been enabled for all the Tegra platforms, to start with.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The 'impl' variable is guarded by the symbol DEBUG, but used in an INFO
level print statement. INFO is defined based on LOG_LEVEL. Hence, builds
would fail when
 - DEBUG=0 && LOG_LEVEL>=LOG_LEVEL_INFO with a variable used but not defined
 - DEBUG=1 && LOG_LEVEL<LOG_LEVEL_INFO with a variable defined but not used

Fixing this by guarding impl with the same condition that guards INFO.

Fixes ARM-software/tf-issues#490
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

For SoCs T132 and T210, the header file 'platform_def.h' used to include
'tegra_def.h' and vice versa. This patch breaks this circular dependency
by making 'tegra_def.h' independent.

Change-Id: I45a00a84e6ab8b93d5e9242a9ff65f03e9102a96
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by FreeBSD have not been modified.

[0]: https://spdx.org/



Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

This patch implements the handler to calculate the cluster and
system power states for the Tegra210 SoC. The power states
returned by this handler are used by the PSCI library to decide
cache maintenance operations - cluster v cpu.

Change-Id: I93e4139d4cd8a086b51f328e9a76e91428ebcdab
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch fixes the logic used to calculate the end of NS memory
aperture. The functions allows zero sized NS apertures as that is
a valid requirement for some use cases. e.g. VPR resize.

Change-Id: Ie966e0ea2f9c6888d21c38e734003704094b3720
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The video memory carveout has to be re-sized depending on the Video
content. This requires the NS world to send us new base/size values.
Before setting up the new region, we must zero out the previous memory
region, so that the video frames are not leaked to the outside world.

This patch adds the logic to zero out the previous memory carveout
region.

Change-Id: I471167ef7747154440df5c1a5e015fbeb69d9043
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Earlier, we were setting "System Suspend" as the power state for all system
states. This caused incorrect system state during a cluster power down.

This patch fixes this anomaly and sets the correct power state during a
cluster/system power down.

Change-Id: Ibd002930e0ae103e381e0a19670c3c4d057e7cb7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds max retries for all ARI requests and asserts
if the ARI request is still busy.

Change-Id: I454ad9b557bb59e513e4c0c6f071275c87d0e07a
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds the Tegra micro-seconds controller to the
memory map. This allows us to use the delay_timer functionality.

Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch moves the platform delay timer init to early BL31
platform setup, so that platforms can use the udelay/mdelay
routines in the early init code.

Change-Id: I6fe20b76176ea22589539c180c5b6f9d09eda8de
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

One assert depends on code that is conditionally compiled based on the
DEBUG define. This patch modifies the conditional inclusion of such code
so that it is based on the ENABLE_ASSERTIONS build option.

Change-Id: Ic5659a3db8632593b9d2e83dac6d30afd87c131d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch enables the assert in the context save routine
by default, for all flavours of the build.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch changes the platform Makefile to set `ENABLE_ASSERTIONS` to
1 instead of the deprecated option `ASM_ASSERTION`. This also pulls in
C assertions in release mode.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch groups all the platform configuration macros into
the common platform.mk makefile.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch sanity checks the SMMU context created by the platform
code. The first entry contains the size of the array; which the
driver now verifies before moving on with the save.

This patch also fixes an error in the calculation of the size of
the context that gets copied to TZDRAM.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch fixes the size used to save the context, when the
device enters System Suspend.

Reported by: David Cunado
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

On Tegra systems, there are multiple software components that
require to interact with MCE. The components can either be 32-bit
or 64-bit payloads. This patch supports MCE SMC functions ID for
AARCH32 and AARCH64 architectures to support such clients.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch stops initialising the same UART console, as a "crash"
console. The normal and the crash consoles use the same UART port
and hence the crash console init function now only checks if the
console is ready to be used.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds support for fake system suspend (SC7).
This is a debug mode, to ensure that a different code path is
executed for cases like pre-silicon development, where a
full-fledged SC7 is not possible in early stages.

This particular patch ensures that, if fake system suspend is
enabled (denoted by tegra_fake_system_suspend variable
having a non-zero value), instead of calling WFI, a request
for a warm reset is made for starting the SC7 exit procedure.

This ensures that the code path of kernel->ATF and back to
kernel is executed without depending on other components
involved in SC7 code path.

Additionally, this patch also adds support for SMC call
from kernel, enabling fake system suspend mode.
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch restores the MC_TXN_OVERRIDE settings when we exit from
System Suspend.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

During boot, USB3 and flash media (SDMMC/SATA) devices need access to
IRAM. Because these clients connect to the MC and do not have a direct
path to the IRAM, the MC implements AHB redirection during boot to allow
path to IRAM. In this mode, accesses to a programmed memory address aperture
are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
initialized to disable this aperture. Once bootup is complete, we must
program IRAM base/top, thus disabling access to IRAM.

This patch provides functionality to disable this access. The tegra port
calls this new function before jumping to the non-secure world during
cold boot.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds support to read the chip id and identify if
the current platform is Tegra186.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch programs MC transaction overrides settings using
mc_txn_override_cfgs array for all Tegra chips beyond Tegra186
rev. A01
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

GCC version 4.8 (and presumably earlier) warn when non-standard types are
used for bitfield definitions when -pedantic is enabled. This prevents TF
from being built with such toolchains, since -Werror -pedantic options are
used.

gcc-4.9 removed this warning; -pedantic is intended to cause gcc to emit a
warning in all cases required by the standard, but the standard does not
require a warning in this case.

See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57773

Signed-off-by: Stephen Warren <swarren@nvidia.com>

This patch adds flexibility to the code to initialise multiple SMMU
devices. The base address macro name has been changed to make it
explicit that we support multiple SMMUs.

Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch empowers the platforms to provide an array with the
registers that must be saved/restored across System Suspend.
Original-change-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch enables the 'xlat_table_v2' library for the Tegra Memory
Controller driver. This library allows us to dynamically map/unmap
memory regions, with MMU enabled.

The Memory Controller driver maps/unmaps non-overlapping Video Memory
region, to clean it of any secure contents, before it resizes the
region.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch makes the default implementation of plat_core_pos_by_mpidr()
as weakly linked, so that platforms can override it with their own.

Tegra186, for one, does not have CPU IDs 2 and 3, so it has its own
implementation of plat_core_pos_by_mpidr().

Change-Id: I7a5319869c01ede3775386cb95af1431792f74b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch empowers the platforms to provide the settings (e.g. stream ID,
security setting, transaction overrides) required by the Memory Controller
driver. This allows the platforms to program the Memory Controller as per
their needs and makes the driver scalable.
Original-change-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch removes the memory controller configuration setting, which
allowed non-secure access to the TZSRAM memory.

Change-Id: Ic13645ba6a7694f192565962df40ca4fb8130f23
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>