- 26 Jun, 2017 3 commits
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Dimitris Papastamos authored
On Juno AArch32, the L2 cache may contain garbage after the warm reset from AArch64 to AArch32. This is all fine until the MMU is configured and the data caches enabled. To avoid fetching stale data from the L2 unified cache, invalidate it before the warm reset to AArch32 state. Change-Id: I7d27e810692c02c3e83c9f31de67f6bae59a960a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Dimitris Papastamos authored
Before BL2 loads the SCP ram firmware, `SCP_BOOT_CFG_ADDR` specifies the primary core. After the SCP ram firmware has started executing, `SCP_BOOT_CFG_ADDR` is modified. This is not normally an issue but the Juno AArch32 boot flow is a special case. BL1 does a warm reset into AArch32 and the core jumps to the `sp_min` entrypoint. This is effectively a `RESET_TO_SP_MIN` configuration. `sp_min` has to be able to determine the primary core and hence we need to restore `SCP_BOOT_CFG_ADDR` to the cold boot value before `sp_min` runs. This magically worked when booting on A53 because the core index was zero and it just so happened to match with the new value in `SCP_BOOT_CFG_ADDR`. Change-Id: I105425c680cf6238948625c1d1017b01d3517c01 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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davidcunado-arm authored
Fix FWU and cache helper optimization
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- 23 Jun, 2017 3 commits
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davidcunado-arm authored
psci: minor fixes in lib
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davidcunado-arm authored
aarch64: Enable Statistical Profiling Extensions for lower ELs
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davidcunado-arm authored
Fully initialise essential control registers
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- 22 Jun, 2017 6 commits
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Etienne Carriere authored
Call svc_suspend_finish if registered. psci_get_stat() is static to psci_stat.c Fix types used in comparison. Fix coding style (empty line between variable definition and instructions block). Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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davidcunado-arm authored
aarch32: Apply workaround for errata 813419 of Cortex-A57
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Dimitris Papastamos authored
TLBI instructions for monitor mode won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. NOTE: This workaround is present in AArch64 TF and already enabled by default on Juno. Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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davidcunado-arm authored
uniphier: embed ROTPK hash into BL1/BL2
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davidcunado-arm authored
plat: Hikey960: fix the CPU hotplug
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dp-arm authored
SPE is only supported in non-secure state. Accesses to SPE specific registers from SEL1 will trap to EL3. During a world switch, before `TTBR` is modified the SPE profiling buffers are drained. This is to avoid a potential invalid memory access in SEL1. SPE is architecturally specified only for AArch64. Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 21 Jun, 2017 3 commits
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David Cunado authored
This patch updates the el3_arch_init_common macro so that it fully initialises essential control registers rather then relying on hardware to set the reset values. The context management functions are also updated to fully initialise the appropriate control registers when initialising the non-secure and secure context structures and when preparing to leave EL3 for a lower EL. This gives better alignement with the ARM ARM which states that software must initialise RES0 and RES1 fields with 0 / 1. This patch also corrects the following typos: "NASCR definitions" -> "NSACR definitions" Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc Signed-off-by: David Cunado <david.cunado@arm.com>
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Soby Mathew authored
This patch enables cache helper functions `flush_dcache_range`, `clean_dcache_range` and `invalidate_dcache_range` to exit early if the size argument specified is zero Change-Id: I0b63e8f4bd3d47ec08bf2a0b0b9a7ff8a269a9b0 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Soby Mathew authored
This patch fixes the following issues in Firmware Update (FWU) code: 1. The FWU layer maintains a list of loaded image ids and while checking for image overlaps, INVALID_IMAGE_IDs were not skipped. The patch now adds code to skip INVALID_IMAGE_IDs. 2. While resetting the state corresponding to an image, the code now resets the memory used by the image only if the image were copied previously via IMAGE_COPY smc. This prevents the invalid zeroing of image memory which are not copied but are directly authenticated via IMAGE_AUTH smc. Change-Id: Idf18e69bcba7259411c88807bd0347d59d9afb8f Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 20 Jun, 2017 15 commits
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davidcunado-arm authored
aarch32: Implement errata workarounds for Cortex A53 and A57
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Masahiro Yamada authored
Currently, ROTPK_NOT_DEPLOYED flag is set in plat_get_rotpk_info(). It is up to users how to retrieve ROTPK if the ROT verification is desired. This is not nice. This commit improves plat_get_rotpk_info() implementation and automates the ROTPK deployment. UniPhier platform has no ROTPK storage, so it should be embedded in BL1/BL2, like ARM_ROTPK_LOCATION=devel_rsa case. This makes sense because UniPhier platform implements its internal ROM i.e. BL1 is used as updatable pseudo ROM. Things work like this: - ROT_KEY (default: $(BUILD_PLAT)/rot_key.pem) is created if missing. Users can override ROT_KEY from the command line if they want to use a specific ROT key. - ROTPK_HASH is generated based on ROT_KEY. - ROTPK_HASH is included by uniphier_rotpk.S and compiled into BL1/BL2. - ROT_KEY is input to cert_create tool. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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davidcunado-arm authored
xlat_tables_v2: fix signed/unsigned comparisons
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Dimitris Papastamos authored
Commit 6de8b24f broke Juno AArch32 build. Change-Id: Ied70d9becb86e53ccb46a2e3245e2a551d1bf701 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Dimitris Papastamos authored
Fixes ARM-software/tf-issues#495 Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Dimitris Papastamos authored
This brings the implementation on par with the software errata workarounds for AArch64. Change-Id: I98a85fd92e32ae4259f4ec5b3e93cffc87090064 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Dimitris Papastamos authored
This brings the implementation on par with the software errata workarounds for AArch64. Change-Id: Id103602e35b1c0ad3705a5b2b7cdb34dd8a8c5e2 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Dimitris Papastamos authored
Helper function to assist with errata workaround application. Change-Id: Idba42ca238442cc826f43444dbfa754e433a5e5e Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Dimitris Papastamos authored
Flush the console so the errata report is printed correctly before exit to normal world. Change-Id: Idd6b5199b5fb8bda9d16a7b5c6426cdda7c73167 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Dimitris Papastamos authored
On ARM platforms before exiting from SP_MIN ensure that the default console is switched to the runtime serial port. Change-Id: I0ca0d42cc47e345d56179eac16aa3d6712767c9b Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Varun Wadekar authored
This patch changes input param level in xlat_tables_print_internal() to an unsigned int to fix the signed/unsigned comparison warnings. The compiler complains about these warnings, thus halting the build flow for Tegra platforms. Change-Id: Ieccc262a63daca7a26ca6a14d81466397af8b89f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: David Cunado <david.cunado@arm.com>
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davidcunado-arm authored
Resolve build errors flagged by GCC 6.2
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David Cunado authored
With GCC 6.2 compiler, more C undefined behaviour is being flagged as warnings, which result in build errors in ARM TF build. This patch addresses issue caused by enums with values that exceed maximum value for an int. For these cases the enum is converted to a set of defines. Change-Id: I5114164be10d86d5beef3ea1ed9be5863855144d Signed-off-by: David Cunado <david.cunado@arm.com>
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davidcunado-arm authored
hikey960: migrate to use A53 specific defines
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David Cunado authored
The patch fb7d32e5 migrated the CPU libraries to have unique defines, prefixing them with the CPU name. This patch migrates the hikey960 platform port to use the A53 specific defines. Change-Id: Id76f544b0b236bbd4974ab5ffa1203f073c20021 Signed-off-by: David Cunado <david.cunado@arm.com>
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- 19 Jun, 2017 1 commit
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Leo Yan authored
In CPU off callback function, the old code uses the function hisi_test_pwrdn_allcores() to check if all CPUs in cluster have been powered off and if it's valid then power off the whole cluster. But the function hisi_test_pwrdn_allcores() only maintains the different power states only for CPU suspend/resume flow, so it cannot return correct states for CPU on/off flow. This patch is to change use hisi_test_cpu_down() to check if all CPUs have been powered off, so that can power off the whole cluster properly when all CPUs in cluster have been hotplugged off. Signed-off-by: Tao Wang <kevin.wangtao@hisilicon.com> Signed-off-by: Leo Yan <leo.yan@linaro.org>
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- 16 Jun, 2017 3 commits
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davidcunado-arm authored
Tegra misra fixes v1
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davidcunado-arm authored
uniphier memory-overrun bug fix
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davidcunado-arm authored
CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is set
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- 15 Jun, 2017 6 commits
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davidcunado-arm authored
tools: Use exported quiet flag from top-level Makefile
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davidcunado-arm authored
Fix coverity error in CSS SCMI driver
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davidcunado-arm authored
hikey960: remove mailbox driver
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jagadeesh ujja authored
The ARM_PLAT_MT bit enables the support for MT bit in MPIDR format. This means that the level 0 affinity represents the thread and CPU / Cluster levels are at affinity level 1 and 2 respectively. This was not catered for in the scpi 'css_scp_get_power_state, API. Since the SCPI driver can only cater for single threaded CPUs, this patch fixes the problem by catering for this shift by effectively ignoring the Thread (level 0) affinity level. Change-Id: If44f55c9fb2773c8d3f8a9bbcf5420a6f7409dfe Signed-off-by: jagadeesh ujja <jagadeesh.ujja@arm.com>
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Haojian Zhuang authored
Since this mailbox driver is abandoned, remove it. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Masahiro Yamada authored
Check the array index before the write. This issue was found by a static analysis tool. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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