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"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"

This is treated as an error since commit 93c690eb

 ("Enable
-Wshift-overflow=2 to check for undefined shift behavior")

Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.

This patch fixes the sequence so that DMCs are set to CONFIG
state before writing to ERR0CTLR0 register and moved back to
READY state after writing.

Change-Id: I1252f3ae0991603bb29234029cddb5fbf869c1b2
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

The watchdog is configured with a default value of 256 seconds in order
to implement the Trusted Board Boot Requirements.

For the FVP and Juno platforms, the FWU process relies on a watchdog
reset. In order to automate the test of FWU, the length of this process
needs to be as short as possible. Instead of waiting for those 4 minutes
to have a reset by the watchdog, tell it to reset immediately.

There are no side effects as the value of the watchdog's load register
resets to 0xFFFFFFFF.

Tested on Juno.

Change-Id: Ib1aea80ceddc18ff1e0813a5b98dd141ba8a3ff2
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

The AArch32 system registers are not listed if the platform supports
AArch64 only.

Change-Id: I087a10ae6e7cad1bb52775a344635dbac1f12679
Signed-off-by: Imre Kis <imre.kis@arm.com>

Add uml sequence and class diagram to illustrate the behavior of the
storage abstraction layer.

Change-Id: I338262729f8034cc3d3eea1d0ce19cca973a91bb
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef

When pointer authentication is enabled, the LR value saved on the stack
contains a Pointer Authentication Code (PAC). It must be stripped to
retrieve the return address.

The PAC field is stored on the high bits of the address and defined as:
- PAC field = Xn[54:bottom_PAC_bit], when address tagging is used.
- PAC field = Xn[63:56, 54:bottom_PAC_bit], without address tagging.

With bottom_PAC_bit = 64 - TCR_ELx.TnSZ

Change-Id: I21d804e58200dfeca1da4c2554690bed5d191936
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

* changes:
  rcar_gen3: drivers: ddr-a: Fix E3 DDR init coding style
  rcar_gen3: drivers: ddr-a: Pass ddrBackup around
  rcar_gen3: drivers: ddr-a: Inline ddr_init_e3.h
  rcar_gen3: drivers: ddr-a: Fix V3M DDR init coding style
  rcar_gen3: drivers: ddr-a: Fix D3 DDR init coding style
  rcar_gen3: drivers: ddr-a: Replace {Read,Write}Reg_32() with mmio_{read,write}_32()
  rcar_gen3: drivers: ddr-a: Unify register definitions

Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.

Currently with this patch only the primary CPU is booted
and the rest of them wait for an interrupt.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab

Update the skeleton implementation of the console interface.

The 32 bit version was outdated and has been copied from the 64 bit
version.

Change-Id: Ib3e4eb09402ffccb1a30c703a53829a7bf064dfe
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

* changes:
  Enable -Wshift-overflow=2 to check for undefined shift behavior
  Update base code to not rely on undefined overflow behaviour
  Update hisilicon drivers to not rely on undefined overflow behaviour
  Update synopsys drivers to not rely on undefined overflow behaviour
  Update imx platform to not rely on undefined overflow behaviour
  Update mediatek platform to not rely on undefined overflow behaviour
  Update layerscape platform to not rely on undefined overflow behaviour
  Update intel platform to not rely on undefined overflow behaviour
  Update rockchip platform to not rely on undefined overflow behaviour
  Update renesas platform to not rely on undefined overflow behaviour
  Update meson platform to not rely on undefined overflow behaviour
  Update marvell platform to not rely on undefined overflow behaviour

Coding style cleanup, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I689418768e87a8c1b6eeeb9f1a48dfb333908017

Pass the ddrBackup variable around instead of making it a global variable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ib796181247712e464b77f5f8be5f851745727d74
---
NOTE: The camelcase is fixed in later patch.

Partly inline ddr_init_e3.h into ddr_init_e3.c . Drop duplicate
INITDRAM_* macros, which are defined in boot_init_dram.h .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I758661d337a86b6a07f82cd4067fbc149cbaed1e

Coding style cleanup, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I4f3e3812ffaa24fec50857756539b563eff33cdd

Coding style cleanup, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9b26b838e8c45d9b4f53c67663ec94002dd9edfe

Replace ad-hoc register accessors with generic ones, remove the ad-hoc
implementation. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I21446a00a38c6a39d6a48652c34f59814074e831

Unify boot_init_dram_regdef_*.h into boot_init_dram_regdef.h and
clean up it's coding style a bit.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Iae3375969c05f80209ebf7b1ebc3633a7f6317ff

Remove the ad-hoc BITn macros and replace them with generic BIT(n) macro.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I5d0b44d6cba5a69895fed505f6ff780d3574907f

Fix the header file path
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I73a92a3f0049ecbda7eade452405927c04048e01

Currently we have some pre-rendered versions of certain diagrams
in SVG format. These diagrams have corresponding PlantUML source
that can be rendered automatically as part of the documentation
build, removing the need for any intermediate files.

This patch adds the Sphinx "plantuml" extension, replaces
references to the pre-rendered SVG files within the documents,
and finally removes the SVG files and helper script.

New requirements for building the docs are the
"sphinxcontrib-plantuml" Python module (added to the pip
requirements.txt file) and the Graphviz package (provides the
"dot" binary) which is in the Ubuntu package repositories.

Change-Id: I24b52ee40ff79676212ed7cff350294945f1b50d
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

* changes:
  rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.4
  rcar_gen3: drivers: rpc: Modify PFC code
  rcar_gen3: drivers: rpc: Change RPC PHY calibration setting
  rcar_gen3: drivers: ddr-b: Update DDR setting for H3, M3, M3N
  rcar_gen3: drivers: ddr-a: Update E3 DDR setting

Update the revision number in the revision management file.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I94acd1bb53d9d2453e550e2a13b6391b9088ff8d

Modify PFC code and rename macro of MFIS according to Errata of
Hardware User's Manual
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I0ece522647319286350843bbbe8b8ba8b0ae9bac

Modify RPC code according to Errata of Hardware User's Manual
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I82d0a2136c7f18870842f84c49343977708eef1e