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  1. 30 Mar, 2017 7 commits
    • Varun Wadekar's avatar
      Tegra186: handlers to get BL31 arguments from previous bootloader · 48afb167
      Varun Wadekar authored 
      

This patch overrides the default handlers to get BL31 arguments from the
previous bootloader. The previous bootloader stores the pointer to the
arguments in PMC secure scratch register #53.

BL31 is the first component running on the CPU, as there isn't a previous
bootloader. We set the RESET_TO_BL31 flag to enable the path which assumes
that there are no input parameters passed by the previous bootloader.

Change-Id: Idacc1df292a70c9c1cb4d5c3a774bd796175d5e8
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      48afb167
    • Varun Wadekar's avatar
      Tegra186: delete 'Video Memory Carveout' handling · 962014f5
      Varun Wadekar authored 
      

This patch removes duplicate code from the platform's SiP handler
routine for processing Video Memory Carveout region requests and
uses the common SiP handler instead.

Change-Id: Ib307de017fd88d5ed3c816288327cae750a67806
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      962014f5
    • Varun Wadekar's avatar
      Tegra186: modify the return type for `plat_get_syscnt_freq()` · 512da21a
      Varun Wadekar authored 
      Commit c073fda1

 upstream changed the
return type for `plat_get_syscnt_freq()` from uint64_t to unsigned
long long.

This patch modifies the return type for the Tegra186 platform.

Change-Id: Ic9e5c364b90972265576e271582a4347e5eaa6eb
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      512da21a
    • Varun Wadekar's avatar
      Tegra186: Enable ECC and Parity Protection for A02p SKUs · 1eed3838
      Varun Wadekar authored 
      

This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot,
for Tegra186 A02p SKUs.

Change-Id: I8522a6cb61f5e4fa9e0471f558a0c3ee8078370e
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      1eed3838
    • Varun Wadekar's avatar
      Tegra186: mce: Uncore Perfmon ARI Programming · c11e0ddf
      Varun Wadekar authored 
      

Uncore perfmon appears to the CPU as a set of uncore perfmon registers
which can be read and written using the ARI interface. The MCE code
sequence handles reads and writes to these registers by manipulating
the underlying T186 uncore hardware.

To access an uncore perfmon register, CPU software writes the ARI
request registers to specify

* whether the operation is a read or a write,
* which uncore perfmon register to access,
* the uncore perfmon unit, group, and counter number (if necessary),
* the data to write (if the operation is a write).

It then initiates an ARI request to run the uncore perfmon sequence in
the MCE and reads the resulting value of the uncore perfmon register
and any status information from the ARI response registers.

The NS world's MCE driver issues MCE_CMD_UNCORE_PERFMON_REQ command
for the EL3 layer to start the entire sequence. Once the request
completes, the NS world would receive the command status in the X0
register and the command data in the X1 register.

Change-Id: I20bf2eca2385f7c8baa81e9445617ae711ecceea
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      c11e0ddf
    • Varun Wadekar's avatar
      Tegra186: implement `get_target_pwr_state` handler · f3a20c32
      Varun Wadekar authored 
      

This patch implements the `get_target_pwr_state` handler for Tegra186
SoCs. The SoC port uses this handler to find out the cluster/system
state during CPU_SUSPEND, CPU_OFF and SYSTEM_SUSPEND calls.

The MCE firmware controls the power state of the CPU/CLuster/System,
so we query it to get the state and act accordingly.

Change-Id: I86633d8d79aec7dcb405d2301ac69910f93110fe
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      f3a20c32
    • Varun Wadekar's avatar
      Tegra186: mce: add the mce_update_cstate_info() helper function · 87a1df73
      Varun Wadekar authored 
      

This patch adds a helper function to the MCE driver to allow its
clients to issue UPDATE_CSTATE_INFO requests, without having to
setup the CPU context struct.

We introduced a struct to encapsulate the request parameters, that
clients can pass on to the MCE driver. The MCE driver gets the
parameters from the struct and programs the hardware accordingly.

Change-Id: I02bce57506c4ccd90da82127805d6b564375cbf1
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      87a1df73
  3. 27 Mar, 2017 2 commits
  5. 23 Mar, 2017 9 commits
    • Varun Wadekar's avatar
      Tegra186: reset power state info during CPU_ON · b46ac6dc
      Varun Wadekar authored 
      

This patch resets the power state info for CPUs when onlining,
as we set deepest power when offlining a core but that may not
be requested by non-secure sw which controls idle states. It
will re-init this info from non-secure software when the core
come online.

Original change by Prashant Gaikwad <pgaikwad@nvidia.com>

Change-Id: Id6c2fa2b821c7705aafbb561a62348c36fd3abd8
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      b46ac6dc
    • Varun Wadekar's avatar
      Tegra186: enable support for simulation environment · abd3a91d
      Varun Wadekar authored 
      

The Tegra simulation environment has limited capabilities. This patch
checks the chip's major and minor versions to decide the features to
enable/disable - MCE firmware version checking is disabled and limited
Memory Controller settings are enabled

Change-Id: I258a807cc3b83cdff14a9975b4ab4f9d1a9d7dcf
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      abd3a91d
    • Varun Wadekar's avatar
      Tegra186: check MCE firmware version during boot · 5cb89c56
      Varun Wadekar authored 
      

This patch checks that the system is running with the supported MCE
firmware during boot. In case the firmware version does not match the
interface header version, then the system halts.

Change-Id: Ib82013fd1c1668efd6f0e4f36cd3662d339ac076
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5cb89c56
    • Varun Wadekar's avatar
      Tegra186: fix programming sequence for SC7/SC8 entry · 50f38a4a
      Varun Wadekar authored 
      

This patch fixes the programming sequence for 'System Suspend' and
'Quasi power down' state entry. The device needs to update the
required power state before querying the MCE firmware to see the
entry to that power state is allowed.

Original change by Allen Yu <alleny@nvidia.com>

Change-Id: I65e03754322188af913fabf41f29d1c3595afd85
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      50f38a4a
    • Varun Wadekar's avatar
      Tegra186: program default core wake mask during CPU_SUSPEND · 1b9ab054
      Varun Wadekar authored 
      

This patch programs the default CPU wake mask during CPU_SUSPEND. This
reduces the CPU_SUSPEND latency as the system has to send one less SMC
before issuing the actual suspend request.

Original change by Krishna Sitaraman <ksitaraman@nvidia.com>

Change-Id: I1f9351dde4ab30936070e9f42c2882fa691cbe46
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      1b9ab054
    • Varun Wadekar's avatar
      Tegra186: clear the system cstate for offline core · c60f58ef
      Varun Wadekar authored 
      

This patch clears the system cstate when offlining a CPU core as we
need to update the sytem cstate to SC7 only when we enter system
suspend.

Original change by Prashant Gaikwad <pgaikwad@nvidia.com>

Change-Id: I1cff9bbab4db7d390a491c8939aea5db6c6b5c59
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      c60f58ef
    • Varun Wadekar's avatar
      Tegra186: mce: enable LATIC for chip verification · 66ec1125
      Varun Wadekar authored 
      

This patch adds a new interface to allow for making an ARI call that
will enable LATIC for the chip verification software harness.

LATIC allows some MINI ISMs to be read in the CCPLEX. The ISMs are
used for various measurements relevant ot particular locations in
Silicon. They are small counters which can be polled to determine
how fast a particular location in the Silicon is.

Original change by Guy Sotomayor <gsotomayor@nvidia.com>

Change-Id: Ifb49b8863a009d4cdd5d1ba38a23b5374500a4b3
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      66ec1125
    • Varun Wadekar's avatar
      Tegra186: save/restore BL31 context to/from TZDRAM · 68c7de6f
      Varun Wadekar authored 
      

This patch adds support to save the BL31 state to the TZDRAM
before entering system suspend. The TZRAM loses state during
system suspend and so we need to copy the entire BL31 code to
TZDRAM before entering the state.

In order to restore the state on exiting system suspend, a new
CPU reset handler is implemented which gets copied to TZDRAM
during boot. TO keep things simple we use this same reset handler
for booting secondary CPUs too.

Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      68c7de6f
    • Varun Wadekar's avatar
      Tegra186: re-configure MSS' client settings · e64ce3ab
      Varun Wadekar authored 
      

This patch reprograms MSS to make ROC deal with ordering of
MC traffic after boot and system suspend exit. This is needed
as device boots with MSS having all control but POR wants ROC
to deal with the ordering. Performance is expected to improve
with ROC but since no one has really tested the performance,
keep the option configurable for now by introducing a platform
level makefile variable.

Change-Id: I2e782fea138ccf9d281eb043a6b2c3bb97c839a7
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e64ce3ab
  7. 22 Mar, 2017 2 commits
    • Varun Wadekar's avatar
      Tegra186: implement support for System Suspend · 50402b17
      Varun Wadekar authored 
      

This patch adds the chip level support for System Suspend entry
and exit. As part of the entry sequence we first query the MCE
firmware to check if it is safe to enter system suspend. Once
we get a green light, we save hardware block settings and enter
the power state. As expected, all the hardware settings are
restored once we exit the power state.

Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      50402b17
    • Varun Wadekar's avatar
      Tegra186: smmu: driver for the smmu hardware block · 4122151f
      Varun Wadekar authored 
      

This patch adds a device driver for the SMMU hardware block on
Tegra186 SoCs. We use the generic ARM SMMU-500 IP block on
Tegra186. The driver only supports saving the SMMU settings
before entering system suspend. The MC driver and the NS world
clients take care of programming their own settings.

Change-Id: Iab5a90310ee10f6bc8745451ce50952ab3de7188
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      4122151f
  9. 20 Mar, 2017 18 commits
  11. 07 Mar, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs · 1f38d3c9
      Varun Wadekar authored 
      

This patch enables the following erratas for the Tegra210 SoC:

* Cortex-A57
=============
- A57_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A57_826974
- ERRATA_A57_826977
- ERRATA_A57_828024
- ERRATA_A57_829520
- ERRATA_A57_833471

* Cortex-A53
=============
- A53_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A53_826319
- ERRATA_A53_836870

Tegra210 uses Cortex-A57 revision: r1p1 and Cortex-A53 revision: r0p2.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      1f38d3c9
  13. 02 Mar, 2017 1 commit