- 20 Apr, 2021 31 commits
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Lad Prabhakar authored
Add pin control support for RZ/G2E SoC. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I736724cc0dd32f2169018ed7f2f48319b039b61f
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Lad Prabhakar authored
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the same. Signed-off-by:
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Lad Prabhakar authored
Add support to identify HopeRun HiHope RZ/G2N board. Signed-off-by:
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Lad Prabhakar authored
Select MMC_CH1 for eMMC on RZ/G2N SoC. Signed-off-by:
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Lad Prabhakar authored
Add QoS support for RZ/G2N SoC. Signed-off-by:
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Lad Prabhakar authored
Add pin control support for RZ/G2N SoC. Signed-off-by:
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Lad Prabhakar authored
Add support for initializing DRAM on RZ/G2N SoC. Signed-off-by:
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Lad Prabhakar authored
Add support to identify HopeRun HiHope RZ/G2H board. Signed-off-by:
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Lad Prabhakar authored
Select MMC_CH1 for eMMC on RZ/G2H SoC. Signed-off-by:
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Lad Prabhakar authored
Add QoS support for RZ/G2H SoC. Signed-off-by:
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Lad Prabhakar authored
Add pin control support for RZ/G2H SoC. Signed-off-by:
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Lad Prabhakar authored
Add support for initializing DRAM on RZ/G2H SoC. Signed-off-by:
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Lad Prabhakar authored
Switch using common ddr driver code from renesas/common/ddr directory for RZ/G2M SoC. Signed-off-by:
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Lad Prabhakar authored
Move ddr driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Madhukar Pappireddy authored
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Manish Pandey authored
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Manish Pandey authored
* changes: plat/marvell: remove subversion from Marvell make files drivers/marvell: check if TRNG unit is present plat/marvell: a8k: move efuse definitions to separate header plat/marvell/armada: fix TRNG return SMC handling drivers: marvell: comphy: add rx training on 10G port plat/marvell/armada: postpone MSS CPU startup to BL31 stage plat: marvell: armada: a8k: Fix LD selector mask plat/marvell/armada: allow builds without MSS support drivers: marvell: misc-dfx: extend dfx whitelist drivers: marvell: add support for secure read/write of dfx register-set ddr_phy: use smc calls to access ddr phy registers drivers: marvell: thermal: use dedicated function for thermal SiPs drivers: marvell: add thermal sensor driver and expose it via SIP service fix: plat: marvell: fix MSS loader for A8K family
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Konstantin Porotchkin authored
Subversion is not reflecting the Marvell sources variant anymore. This patch removes version.mk from Marvell plafroms. Signed-off-by:Konstantin Porotchkin <kostap@marvell.com> Change-Id: I8f3afbe3fab3a38da68876f77455f449f5fe0179
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Konstantin Porotchkin authored
Some Marvell SoCs may have crypto engine disabled in the HW. This patch checks the AP LD0 efuse for crypto engine/TRNG presence before initializing the driver. Change-Id: I441e7c69a137106bd36302b028b04c0b31896dbd Signed-off-by:
sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by:
Yi Guo <yi.guo@cavium.com>
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Konstantin Porotchkin authored
Move efuse definitions to a separate header file for later usage with other FW modules. Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f Signed-off-by:
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Konstantin Porotchkin authored
Use single 64b register for the return value instead of two 32b. Report an error if caller requested larger than than 64b random number in a single SMC call. Signed-off-by:
Nadav Haklai <nadavh@marvell.com>
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Alex Evraev authored
This patch forces rx training on 10G ports as part of comphy_smc call from Linux. Signed-off-by:
Alex Evraev <alexev@marvell.com> Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763 Tested-by:
Stefan Chulski <stefanc@marvell.com> Reviewed-by:
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Konstantin Porotchkin authored
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations. Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by:
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Guo Yi authored
Fixed a bug that the actually bit number was used as a mask to select LD0 or LD1 fuse Signed-off-by:
Guo Yi <yguo@cavium.com> Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146 Tested-by:
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Konstantin Porotchkin authored
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2 definition. Images build with MSS_SUPPORT=0 will not include service CPUs FW and will not support PM, FC and other features implemented in these FW images. Signed-off-by:
Ofer Heifetz <oferh@marvell.com> Reviewed-by:
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Grzegorz Jaszczyk authored
Linux cpu clk driver requires access to some dfx registers. By adding these registers to the white list, we enable access to them from non-secure world. Change-Id: Ic05c96b375121c025bfb41c2ac9474a530720155 Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25187 Tested-by:
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Grzegorz Jaszczyk authored
Since the dfx register set is going to be marked as secure expose dfx secure read and write function via SiP services. In introduced misc_dfx driver some registers are white-listed so non-secure software can still access them. This will allow non-secure word drivers access some white-listed registers related to e.g.: Sample at reset, efuses, SoC type and revision ID accesses. Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0 Signed-off-by:
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Alex Leibovich authored
Added smc calls support to access ddr phy registers. Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870 Signed-off-by:
Alex Leibovich <alexl@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20791 Tested-by:
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Grzegorz Jaszczyk authored
Since more drivers which uses dfx register set need to be handled with use of SiP services, use dedicated and more meaningful name for thermal SiP services. Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f Signed-off-by:
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Grzegorz Jaszczyk authored
Since the dfx register set is going to be marked as secure (in order to protect efuse registers for non secure access), accessing thermal registers which are part of dfx register set, will not be possible from lower exception levels. Due to above expose thermal driver as a SiP service. This will allow Linux and U-Boot thermal driver to initialise and perform various operations on thermal sensor. The thermal sensor driver is based on Linux drivers/thermal/armada_thermal.c. Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e Signed-off-by:
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Konstantin Porotchkin authored
Wrong brakets caused MSS FW load timeout error: ERROR: MSS DMA failed (timeout) ERROR: MSS FW chunk 0 load failed ERROR: SCP Image load failed This patch fixes the operator precedence in MSS FW load. Signed-off-by:
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- 19 Apr, 2021 2 commits
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Manish Pandey authored
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Mayur Gudmeti authored
The current SPM_MM implementations expects the SP image addresses as static macros. This means platforms wanting to use dynamically allocated memory addresses are left out. This patch gets sp_boot_info at the beginning of spm_sp_setup function and uses member variables of sp_boot_info to setup the context. So member variables of struct sp_boot_info and consequently the context can be initialized by static macros or dynamiclly allocated memory address.. Change-Id: I1cb75190ab8026b845ae20a9c6cc416945b5d7b9 Signed-off-by:Mayur Gudmeti <mgudmeti@nvidia.com>
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- 16 Apr, 2021 1 commit
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Sandrine Bailleux authored
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- 15 Apr, 2021 2 commits
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Madhukar Pappireddy authored
* changes: drivers/arm/css/scmi: Update power domain protocol version to 2.0 tc0: update GICR base address
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Yidi Lin authored
UART register definition is the same on MediaTek platforms. Move uart.h to common folder and remove the duplicate file. Signed-off-by:Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iea0931dfd606ae4a7ab475b9cb3a08dc6de68b36
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- 14 Apr, 2021 3 commits
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Nicola Mazzucato authored
The SCMI power domain protocol in firmware has been updated to v2.0, thus update the corresponding version in TF-A too. Signed-off-by:Nicola Mazzucato <nicola.mazzucato@arm.com> Change-Id: If3920ff71136dce94b2780e29a47f24aa09876c0
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Usama Arif authored
The number of ITS have changed from 4 to 1, resulting in GICR base address change. Signed-off-by:Usama Arif <usama.arif@arm.com> Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
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Manish V Badarkhe authored
Updated the documentation with latest Mbed TLS supported version i.e. Mbed TLS v2.26.0 Fixes available in this version of Mbed TLS mainly affect key generation/writing and certificates writing, which are features used in the cert_create tool. Release notes of Mbed TLSv2.26.0 are available here: https://github.com/ARMmbed/mbedtls/releases/tag/v2.26.0 Change-Id: Ie15ee45d878b7681e15ec4bf64d54b416a31aa2f Signed-off-by:
Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 13 Apr, 2021 1 commit
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Madhukar Pappireddy authored
* changes: plat:xilinx:versal: Add JTAG DCC support plat:xilinx:zynqmp: Add JTAG DCC support drivers: dcc: Support JTAG DCC console
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