- 18 Jan, 2019 7 commits
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Anthony Zhou authored
Main fixes: Add suffix U for constant [Rule 10.1] Match the operands type [Rule 10.4] Use UL replace U for that constant define that need do "~" operation [Rule 12.4] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: Ia1e814ca3890eab7904be9c79030502408f30936 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
Main fixes: * Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6] * Add function define to header file [Rule 8.4] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: Ifa3ba4e75046697cfede885096bee9a30efe6519 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch reduces the code complexity for the platform's 'get_target_pwr_state' handler, by reducing the number of 'if' conditions and adding helper functions to calculate power state for the cluster/system. Tested with 'pmccabe' Change-Id: I32fa4c814bd97f620f2003fa39f1bfceae563771 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
Main fixes: Add parentheses to avoid implicit operator precedence [Rule 12.1] Fixed if statement conditional to be essentially boolean [Rule 14.4] Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] Voided non c-library functions whose return types are not used [Rule 17.7] Bug 200272157 Change-Id: Ic3ab5a3de95aeb6d2265df940f7fb35ea0f19ab0 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch adds the driver for the general purpose DMA hardware block on newer Tegra SoCs. The GPCDMA is a special purpose DMA used to speed up memory copy operations to/from DRAM and TZSRAM. This patch introduces a macro 'USE_GPC_DMA' to allow platforms to override CPU based memory operations. Change-Id: I3170d409c83b77e785437b1002a8d70188fabbeb Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Samuel Payne authored
This patch removes the logic to set the bit that enables atomic context save/restore when we enter System suspend. The bootrom enables this bit during cold boot and exit from System Suspend, so we can remove this setting from the driver. Change-Id: Id4e08d5048155c970f5e31d9c9dd676c07182ade Signed-off-by: Samuel Payne <spayne@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses[Rule 20.7] Change-Id: Ibdae1d18d299562ca2b96b2318b914601c9926b1 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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- 16 Jan, 2019 26 commits
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Anthony Zhou authored
This patch removes unused type conversions as all the relevant macros now use U()/ULL(), making these explicit typecasts unnecessary. Change-Id: I01fb534649db2aaf186406b1aef6897662b44fe3 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Sam Payne authored
This patch enables L2 error correction and parity protection for Tegra210 on boot and exit from suspend. The previous bootloader sets the boot parameter, indicating ECC reporting, only for B01 SKUs. Change-Id: I6927884d375a64c69e2f1e9aed85f95c5e3cb17c Signed-off-by: Sam Payne <spayne@nvidia.com>
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Harvey Hsieh authored
This patch skips the BTB invalidate workaround for Tegra210-B01 chips, as they have already been fixed in the hardware. To allow the .S file to include macros, add proper guards to tegra_platform.h. Change-Id: I0826d3c54faeffc9cb0709331f47cbdf25d4b653 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
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Krishna Reddy authored
Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO) based on the latest info received from HW team as a part of BW issues debug. SMMU Client config register are obsolete from T186. Clean up the unnecessary register definitions and programming of these registers. Cleanup unnecessary macros as well. Change-Id: I0d28ae8842a33ed534f6a15bfca3c9926b3d46b2 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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Varun Wadekar authored
This patch memmaps all the IRAM memory banks during boot. The BPMP firmware might place the channels in any of the IRAMs, so it is better to map all the banks to avoid surprises. Change-Id: Ia009a65d227ee50fbb23e511ce509daf41b877ee Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch fixes the logic to check if Atomics hardware block is powered on during boot Reported by: Peter De Schrijver <pdeschrijver@nvidia.com> Change-Id: I4a6521bcee37225d1402321151c48fa631776b8a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch updates the macros to include the newly added IRAM memory apertures. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I931daa310d738e8bf966f14e11d0631920e9bdde
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Force operands of an operator to the same type category [Rule 10.4] Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] Change-Id: I4840c3122939f736113d61f1462af3bd7b0b5085 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Fix implicit widening of composite assignment [Rule 10.6] Change-Id: I5840a07f37beefc3326ac56d0b4a4701602bd8a8 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch removes unwanted error prints from the MCE command handler, to reduce the code complexity for this function. Tested with 'pmccabe' Change-Id: I375d289db1df9e119eeb1830210974457c8905a4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes support for the SC8 power state as the feature is no longer required for Tegra186 projects. Change-Id: I622a5ddcffe025b9b798801d09bbb856853befd7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses [Rule 20.7] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix implicit widening of composite assignment [Rule 10.6] Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Force operands of an operator to the same type category [Rule 10.4] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: I758e7ef6d45dd2edf4cd5580e2af15219246e75c Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
* EKS blob size was not passed by as a boot parameter earlier. Its being passed now * If EKS value sent by bootloader is non-zero update the boot parameter from default value to the argument passed by bootloader Change-Id: I65a3091bd2c1c908cc9e81c0aab6489cab02c098 Signed-off-by: Akshay Sharan <asharan@nvidia.com>
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Sam Payne authored
DRBG must be initialized to guarantee SRK has a random value during suspend. This patch add a sequence to generate an SRK on boot and during resume for SE1 and SE2. This SRK value is not saved to PMC scratch, and should be overwitten during atomic suspend. Change-Id: Id5e2dc74a1b462dd6addaec1709fec46083a6e1c Signed-off-by: Sam Payne <spayne@nvidia.com>
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Varun Wadekar authored
This patch adds the driver to communicate with the BPMP processor for power management use cases. BPMP controls the entry into cluster and system power states. The Tegra210 platform port queries the BPMP to calculate the target state for the cluster. In case BPMP does not allow CCx entry, the core enters a power down state. Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
This patch fixes MISRA defects for the MCE driver. * Using logical NOT for bool type function * Using MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS replace MPIDR_CLUSTER_MASK Change-Id: I97e96f172a3c1158646a15a184c273c53a103d63 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
This patch uses int32_t to replace ints, to fix Rule 4.6 of the MISRA standard. Change-Id: I20ac6185929eced684b43da3ef1f8cd5fbddc83d Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
This patch adds (void) for unused function parameters to fix Rule 2.7 of the MISRA standard. Change-Id: Ibc3f10b3bfe73363383b4c28413ab8d99fbc8c89 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Marvin Hsu authored
This patch adds the implementation of the SE atomic context save sequence. The atomic context-save consistently saves to the TZRAM carveout; thus there is no need to declare context save buffer or map MMU region in TZRAM for context save. The atomic context-save routine is responsible to validate the context-save progress counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error status to ensure the context save procedure complete successfully. Change-Id: Ic80843902af70e76415530266cb158f668976c42 Signed-off-by: Marvin Hsu <marvinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses [Rule 20.7] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix implicit widening of composite assignment [Rule 10.6] Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Harvey Hsieh authored
This patch adds capability to read the boot flag to enable L2 ECC and Parity Protection bit for the Cortex-A57 CPUs. The previous bootloader sets this flag value for the platform. * with some coverity fix: MISRA C-2012 Directive 4.6 MISRA C-2012 Rule 2.5 MISRA C-2012 Rule 10.3 MISRA C-2012 Rule 10.4 Change-Id: Id7303bbbdc290b52919356c31625847b8904b073 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Harvey Hsieh authored
This patch sets up the clock for the UART console, for real Silicon and FPGA platforms. FPGA platforms run the UART clock source at 13MHz, whereas the clock cource runs at 408MHz for real silicon. Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Marvin Hsu authored
This patch adds helper functions to find out the chip ID of the Tegra SoC. Change-Id: Ia3901dc7cdf77d8c23884d1ed38a80dba6a8afde Signed-off-by: Marvin Hsu <marvinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The platform code generates the power domain tree. The handler to retrieve the tree should also reside in the platform code. This patch moves the plat_get_power_domain_tree_desc() to the individual platforms. Change-Id: Iaafc83ed381d83129501111ef655e3c58a8a553f Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
This patch adds support for simulation platforms as well as fixes issues flagged by the MISRA scans. Main MISRA fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix return type doesn't match the function type [Rule 10.3] * Use single return point instead of multiple [Rule 15.5] * Change return type for the tegra_platform_is_x handlers to bool Change-Id: I871b7c37b22942f6c0c2049c14cc626d4a24d81c Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 18 Dec, 2018 2 commits
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Varun Wadekar authored
This patch converts Tegra platforms to support native GICv2 drivers. This involves removes Tegra's GIC driver port platforms to use interrupt_props Change-Id: I83d8a690ff276dd97928dc60824a4fd36999bb30 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds a macro to allow platforms to compile native GICv2 drivers along with Tegra handlers. Change-Id: I8281796c09dae5704cff2daab831395d65e261b7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 08 Nov, 2018 1 commit
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 25 Oct, 2018 1 commit
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Antonio Nino Diaz authored
Even though at this point plat_crash_console_flush is optional, it will stop being optional in a following patch. The console driver of warp7 doesn't support flush, so the implementation is a placeholder. TI had ``plat_crash_console_init`` and ``plat_crash_console_putc``, but they weren't global so they weren't actually used. Also, they were calling the wrong functions. imx8_helpers.S only has placeholders for all of the functions. Change-Id: I8d17bbf37c7dad74e134c61ceb92acb9af497718 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Migrate to bl31_early_platform_setup2(). - Remove references to removed build options. - Replace zeromem16() by zeromem(). - Use private definition of bl31_params_t. This is an incomplete migration, the platform doesn't currently compile. Change-Id: I67fbf2206678be80c3a16692024221a131cec42f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Aug, 2018 1 commit
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Antonio Nino Diaz authored
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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