GitLab

We don't ever expect to load a binary with an STM32 header on the Arm
FVP platform so remove this type of image from the list of
measurements.

Also remove the GPT image type from the list, as it does not get
measured. GPT is a container, just like FIP is. We don't measure the FIP
but rather the images inside it. It would seem logical to treat GPT the
same way.

Besides, only images that get loaded through load_auth_image() get
measured right now. GPT processing happens before that and is handled in
a different way (see partition_init()).

Change-Id: Iac4de75380ed625b228e69ee4564cf9e67e19336
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Change-Id: I04d9439d5967e93896dfdb0f3d7b0aec96c743f9
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.

SDEN can be found here:
https://documentation-service.arm.com/static/603e3733492bde1625aa8780

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c

* changes:
  fix(io_stm32image): invalidate cache on local buf
  refactor(io_stm32image): add header size variable
  fix(io_stm32image): uninitialized variable warning

* changes:
  feat(plat/imx8m): add sdei support for i.MX8MP
  feat(plat/imx8m): add sdei support for i.MX8MN

As there is constraint with the space for the release builds,
remove some of the legacy code.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I5b8b16f34ed8e480f16ab1aeac80b85cdb391852

Add imx_system_reset2 which extends existing SYSTEM_RESET. It provides
architectural reset definitions and vendor-specific resets.
By default warm reset is triggered.

Also refactor existing implementation of wdog reset, add details about
each flag used.

Change-Id: Ia7348c32c385f1c61f8085776e81dd1e38ddda5c
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

* changes:
  refactor(gicv3): use helper functions to get SPI/ESPI INTID limit
  refactor(gicv3): add helper function to get the limit of ESPI INTID

* changes:
  feat(plat/nxp/lx2): add SUPPORTED_BOOT_MODE definition
  feat(plat/nxp/common): add build macro for BOOT_MODE validation checking
  refactor(plat/nxp/common): moved soc make-variables to new soc_common_def.mk
  refactor(plat/nxp/lx216x): clean up platform configure file
  refactor(plat/nxp/common): moved plat make-variables to new plat_common_def.mk

Fix the mapping of SCMI clock specifiers to the clusters they drive.
Also, add CPU cores to cluster mappings.
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Change-Id: I230bea5614de4e29b54e1686b31bf01c0b6aa86c

* changes:
  refactor(plat/nvidia): use SOC_ID defines
  refactor(plat/mediatek): use SOC_ID defines
  refactor(plat/arm): use SOC_ID defines
  feat(plat/st): implement platform functions for SMCCC_ARCH_SOC_ID
  refactor(plat/st): export functions to get SoC information
  feat(smccc): add bit definition for SMCCC_ARCH_SOC_ID

Use helper functions to get SPI and ESPI INTID limit, to remove
several pieces of similar code in gicv3 driver.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Iaf441fe5e333c4260e7f6d98df6fdd931591976d

Add helper function gicv3_get_espi_limit() to get the value of
(maximum extended SPI INTID + 1), so that some duplicated code can be
removed later.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I0355ca2647f872e8189add259f6c47d415494cce

Add macro of SUPPORTED_BOOT_MODE for board lx2160ardb, lx2160aqds,
lx2162aqds.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I4451ca030eca79c9bc5fee928eec497a7f0e878c

1. Added the build macro "add_boot_mode_define".
2. Use the macro to validate current BOOT_MODE against the
   pre-determined list of SUPPORTED_BOOT_MODE, so each platform
   need to define the list: SUPPORTED_BOOT_MODE.
3. Reports error if BOOT_MODE is not in SUPPORTED_BOOT_MODE list,
   or BOOT_MODE is not supported yet althoug it is in SUPPORTED_BOOT_MODE.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I29be60ecdb19fbec1cd162e327cdfb30ba629b07

Move some soc make variables to new soc_common_def.mk,
then it can be reused by other platforms.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ia30bd332c95b6475f1cfee2f03a8ed3892a9568d

Use common code in common file to configure platform.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I72fe22751f12b8a4996a7b9f75fae4c912ea86de

Move some common make variables to new plat_common_def.mk,
then it can be reused by other platforms.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I37bd65b0f8124f63074fa03339f886c2cdb30bd3

The arm-gic.h was a concatenation of arm-gic.h and irq.h from Linux.
Just copy the 2 files here. They both have MIT license which is accepted
in TF-A.
With this alignment, a new macro is added (GIC_CPU_MASK_SIMPLE).
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ib45174f35f1796ebb7f34af861b59810cfb808b0

Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor
could use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I8308c629448bd8adca9d3d25701adcf0c5a6afc2

Add sdei support for i.MX8MN, this is to let jailhouse Hypervisor
could use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ie15fffdd09e1bba1b22334b8ccac2335c96b8b4d

Bumps [trim-newlines](https://github.com/sindresorhus/trim-newlines) from 3.0.0 to 3.0.1.
- [Release notes](https://github.com/sindresorhus/trim-newlines/releases)
- [Commits](https://github.com/sindresorhus/trim-newlines/commits

)

---
updated-dependencies:
- dependency-name: trim-newlines
  dependency-type: indirect
...

Change-Id: Ie7bcbf8a328d43de004c2f2dbe731f865ef0024d
Signed-off-by: dependabot[bot] <support@github.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>

Add helper function gicv3_get_spi_limit() to get the value of (maximum
SPI INTID + 1), so that some duplicated code can be removed later.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I160c8a88fbb71d22790b8999a84afbfba766f5e7

Due to the small OCRAM space used for TF-A, we will
meet imx8mq build failure caused by too small RAM size.
We CANNOT support it in TF-A CI. It does NOT mean that
imx8mq will be dropped by NXP. NXP will still actively
maintain it in NXP official release.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Iad726ffbc4eedc5f6770612bb9750986b9324ae9