1. 17 Feb, 2014 1 commit
    • Jeenu Viswambharan's avatar
      Fix spilled-over BL1 exception vector · 65f0730b
      Jeenu Viswambharan authored
      The SynchronousExceptionA64 vector has gone beyond the 32-instruction
      limit for individual exception vector. This patch splits and relocates
      the exception handler so that it fits into the 32-instruction window.
      
      Change-Id: Ic60c4fc3f09a1cb071d63ff0e58353ecaecbb62f
      65f0730b
  2. 20 Jan, 2014 1 commit
    • Achin Gupta's avatar
      remove empty definition of display_boot_progress() · 5443f2be
      Achin Gupta authored
      This patch replaces the empty definition of display_boot_progress() in
      bl2_main.c with a weak definition. The former allowed bl2 to use the
      early_exceptions(). It is possible to do that with a simple weak
      definition as well.
      
      Change-Id: Idb3f425a5e265f3579b638e3d26bd8c9bb78f80d
      5443f2be
  3. 17 Jan, 2014 3 commits
    • Jeenu Viswambharan's avatar
      Change comments in assembler files to help ctags · 3a4cae05
      Jeenu Viswambharan authored
      Ctags seem to have a problem with generating tags for assembler symbols
      when a comment immediately follows an assembly label.
      
      This patch inserts a single space character between the label
      definition and the following comments to help ctags.
      
      The patch is generated by the command:
      
        git ls-files -- \*.S | xargs sed -i 's/^\([^:]\+\):;/\1: ;/1'
      
      Change-Id: If7a3c9d0f51207ea033cc8b8e1b34acaa0926475
      3a4cae05
    • Harry Liebel's avatar
      Do not trap access to floating point registers · 4f603683
      Harry Liebel authored
      Traps when accessing architectural features are disabled by clearing bits
      in CPTR_EL3 during early boot, including accesses to floating point
      registers. The value of this register was previously undetermined, causing
      unwanted traps to EL3. Future EL3 code (for example, context save/restore
      code) may use floating point registers, although they are not used by current
      code.
      
      Also, the '-mgeneral-regs-only' flag is enabled in the GCC settings to
      prevent generation of code that uses floating point registers.
      
      Change-Id: I9a03675f6387bbbee81a6f2c9ccf81150db03747
      4f603683
    • Dan Handley's avatar
      Update year in copyright text to 2014 · e83b0cad
      Dan Handley authored
      Change-Id: Ic7fb61aabae1d515b9e6baf3dd003807ff42da60
      e83b0cad
  4. 05 Dec, 2013 3 commits
    • Dan Handley's avatar
      Enable third party contributions · ab2d31ed
      Dan Handley authored
      - Add instructions for contributing to ARM Trusted Firmware.
      
      - Update copyright text in all files to acknowledge contributors.
      
      Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5
      ab2d31ed
    • Sandrine Bailleux's avatar
      Properly initialise the C runtime environment · 65f546a1
      Sandrine Bailleux authored
      This patch makes sure the C runtime environment is properly
      initialised before executing any C code.
      
        - Zero-initialise NOBITS sections (e.g. the bss section).
        - Relocate BL1 data from ROM to RAM.
      
      Change-Id: I0da81b417b2f0d1f7ef667cc5131b1e47e22571f
      65f546a1
    • Sandrine Bailleux's avatar
      Various improvements/cleanups on the linker scripts · 8d69a03f
      Sandrine Bailleux authored
        - Check at link-time that bootloader images will fit in memory
          at run time and that they won't overlap each other.
        - Remove text and rodata orphan sections.
        - Define new linker symbols to remove the need for platform setup
          code to know the order of sections.
        - Reduce the size of the raw binary images by cutting some sections
          out of the disk image and allocating them at load time, whenever
          possible.
        - Rework alignment constraints on sections.
        - Remove unused linker symbols.
        - Homogenize linker symbols names across all BLs.
        - Add some comments in the linker scripts.
      
      Change-Id: I47a328af0ccc7c8ab47fcc0dc6e7dd26160610b9
      8d69a03f
  5. 27 Nov, 2013 2 commits
    • Sandrine Bailleux's avatar
      Unmask SError and Debug exceptions. · 3738274d
      Sandrine Bailleux authored
      Any asynchronous exception caused by the firmware should be handled
      in the firmware itself.  For this reason, unmask SError exceptions
      (and Debug ones as well) on all boot paths.  Also route external
      abort and SError interrupts to EL3, otherwise they will target EL1.
      
      Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092
      3738274d
    • Sandrine Bailleux's avatar
      Move generic architectural setup out of blx_plat_arch_setup(). · c10bd2ce
      Sandrine Bailleux authored
      blx_plat_arch_setup() should only perform platform-specific
      architectural setup, e.g. enabling the MMU.  This patch moves
      generic architectural setup code out of blx_plat_arch_setup().
      
      Change-Id: I4ccf56b8c4a2fa84909817779a2d97a14aaafab6
      c10bd2ce
  6. 25 Oct, 2013 1 commit