- 12 Jan, 2020 1 commit
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Varun Wadekar authored
This patch fixes the violations of Rule 21.1 from all the Tegra common header files. Rule 21.1 "#define and #undef shall not be used on a reserved identifier or reserved macro name" Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185
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- 10 Jan, 2020 2 commits
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Deepika Bhavnani authored
NOTE for platform integrators: API `plat_psci_stat_get_residency()` third argument `last_cpu_idx` is changed from "signed int" to the "unsigned int" type. Issue / Trouble points 1. cpu_idx is used as mix of `unsigned int` and `signed int` in code with typecasting at some places leading to coverity issues. 2. Underlying platform API's return cpu_idx as `unsigned int` and comparison is performed with platform specific defines `PLAFORM_xxx` which is not consistent Misra Rule 10.4: The value of a complex expression of integer type may only be cast to a type that is narrower and of the same signedness as the underlying type of the expression. Based on above points, cpu_idx is kept as `unsigned int` to match the API's and low-level functions and platform defines are updated where ever required Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
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Alexei Fedorov authored
This patch removes re-definition of the following FVP build options from plat\arm\board\fvp\fvp_def.h: 'FVP_CLUSTER_COUNT' 'FVP_MAX_CPUS_PER_CLUSTER' 'FVP_MAX_PE_PER_CPU' which are set in platform.mk. This fixes a potential problem when a build option set in platform.mk file can be re-defined in fvp_def.h header file used by other build component with a different makefile which does not set this option. Ref. GENFW-3505. Change-Id: I4288629920516acf2c239c7b733f92a0c5a812ff Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 09 Jan, 2020 3 commits
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Olivier Deprez authored
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Iee7fb43990047b27972e99572ec4b3dc4e5c0423
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Madhukar Pappireddy authored
In further patches, we aim to enable -Wredundant-decls by default. This rearragement of helper macros is necessary to make Coverity tool happy as well as making sure there are no redundant function declarations for PMF related declarations. Also, PMF related macros were added to provide appropriate function declarations for helper APIs which capture PSCI statistics. Change-Id: I36273032dde8fa079ef71235ed3a4629c5bfd981 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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Madhukar Pappireddy authored
In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 08 Jan, 2020 1 commit
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Varun Wadekar authored
The MCE driver's helper functions were using postive values as error codes. This patch updates the functions to return negative values as error codes instead. Some functions are updated to use the right error code. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I3e2ecc30a6272a357e1a22ec850543fde2a694f6
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- 07 Jan, 2020 3 commits
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Ambroise Vincent authored
The reclaim init code functionality relies on forward reference in the linker script. The LLVM linker does not process it correctly. Change-Id: I993aeb9587bfa07af25b60ed823a6a2c5e970c94 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
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Avinash Mehta authored
Point boot address to DDR location for booting A5DS FPGA FIP, Kernel and rootfs are sideloaded to DDR Also move BL2 to higher address in DDR Change-Id: Ia2a57a0bda776a1a0a96bcd3cfb5c6cd2cf4dc04 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
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Avinash Mehta authored
Correct the system, timer and uart frequencies to successfully run the stack on FPGA Correct Cortex-A5MPcore to 8 word granularity for Cache writeback Change-Id: I2c59c26b7dca440791ad39f2297c68ae513da7b6 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
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- 06 Jan, 2020 2 commits
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Marek Vasut authored
Pass DT to OpTee OS, so that OpTee OS can extract NSEC RAM layout from the DT. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I7d5ebae8d7ab9c70f079e30563d66bbd6a8ac7a4
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Marek Vasut authored
Now that DDR drivers are mostly cleaned up , move them out of staging. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I9de63f847a0ef9ac27a79fb0f848c351fd7f4da6
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- 03 Jan, 2020 1 commit
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Vishnu Banavath authored
The SCU connects one to four Cortex-A5/Cortex-A9 processors to the memory system through the AXI interfaces. The SCU functions are to: - maintain data cache coherency between the Cortex-A5/Cortex-A9 processors - initiate L2 AXI memory accesses - arbitrate between Cortex-A5/Cortex-A9 processors requesting L2 accesses - manage ACP accesses. Snoop Control Unit will enable to snoop on other CPUs caches. This is very important when it comes to synchronizing data between CPUs. As an example, there is a high chance that data might be cache'd and other CPUs can't see the change. In such cases, if snoop control unit is enabled, data is synchoronized immediately between CPUs and the changes are visible to other CPUs. This driver provides functionality to enable SCU as well as enabling user to know the following - number of CPUs present - is a particular CPU operating in SMP mode or AMP mode - data cache size of a particular CPU - does SCU has ACP port - is L2CPRESENT Change-Id: I0d977970154fa60df57caf449200d471f02312a0 Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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- 29 Dec, 2019 1 commit
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Samuel Holland authored
Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ia2f69e26e34462e113bc2cad4dcb923e20b8fb95
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- 26 Dec, 2019 2 commits
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Masahiro Yamada authored
All the SoCs in 64-bit UniPhier SoC family support EL2. Just hard-code MODE_EL2 instead of using el_implemented() helper. Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Roger Lu authored
spm resume will restore Vmodem/Vcore voltages back based on the SPM_DVS_LEVEL. Change-Id: I37ff7ce4ba62219c1858acea816c5bc9ce6c493e Signed-off-by: Roger Lu <roger.lu@mediatek.com>
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- 20 Dec, 2019 5 commits
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Paul Beesley authored
The contents of this header have been merged into the spm_mm_svc.h header file. Change-Id: I01530b2e4ec1b4c091ce339758025e2216e740a4 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
Change-Id: I91c192924433226b54d33e57d56d146c1c6df81b Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
Before adding any new SPM-related components we should first do some cleanup around the existing SPM-MM implementation. The aim is to make sure that any SPM-MM components have names that clearly indicate that they are MM-related. Otherwise, when adding new SPM code, it could quickly become confusing as it would be unclear to which component the code belongs. The secure_partition.h header is a clear example of this, as the name is generic so it could easily apply to any SPM-related code, when it is in fact SPM-MM specific. This patch renames the file and the two structures defined within it, and then modifies any references in files that use the header. Change-Id: I44bd95fab774c358178b3e81262a16da500fda26 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
The Secure Partition Manager (SPM) prototype implementation is being removed. This is preparatory work for putting in place a dispatcher component that, in turn, enables partition managers at S-EL2 / S-EL1. This patch removes: - The core service files (std_svc/spm) - The Resource Descriptor headers (include/services) - SPRT protocol support and service definitions - SPCI protocol support and service definitions Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426 Signed-off-by: Paul Beesley <paul.beesley@arm.com> Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
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Paul Beesley authored
There are two different implementations of Secure Partition management in TF-A. One is based on the "Management Mode" (MM) design, the other is based on the Secure Partition Client Interface (SPCI) specification. Currently there is a dependency between their build flags that shouldn't exist, making further development harder than it should be. This patch removes that dependency, making the two flags function independently. Before: ENABLE_SPM=1 is required for using either implementation. By default, the SPCI-based implementation is enabled and this is overridden if SPM_MM=1. After: ENABLE_SPM=1 enables the SPCI-based implementation. SPM_MM=1 enables the MM-based implementation. The two build flags are mutually exclusive. Note that the name of the ENABLE_SPM flag remains a bit ambiguous - this will be improved in a subsequent patch. For this patch the intention was to leave the name as-is so that it is easier to track the changes that were made. Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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- 19 Dec, 2019 1 commit
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Alexei Fedorov authored
This patch fixes the bug in BL2 dynamic configuration initialisation which prevents loading NT_FW_CONFIG image (ref. GENFW-3471). It also adds parentheses around 'if' statement conditions to fix Coverity defect. Change-Id: I353566c29b84341887e13bf8098a4fedfc4e00ff Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 18 Dec, 2019 2 commits
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Varun Wadekar authored
This patch saves the boot parameters provided by the previous bootloader during cold boot and passes them to Trusty. Commit 06ff251e introduced the plat_trusty_set_boot_args() handler, but did not consider the boot parameters passed by the previous bootloader. This patch fixes that anomaly. Change-Id: Ib40dcd02b67c94cea5cefce09edb0be4a998db37 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Ambroise Vincent authored
Provide an SMC interface to the 9p filesystem. This permits accessing firmware drivers through a common interface, using standardized read/write/control operations. Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I9314662314bb060f6bc02714476574da158b2a7d
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- 17 Dec, 2019 16 commits
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Varun Wadekar authored
This patch enables per-CPU GIC CPU interfaces during CPU power on. The previous code initialized the distributor for all CPUs, which was not required. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ifd957b2367da06405b4c3e2225411adbaec35bb8
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Bence Szépkúti authored
Ported the pmf asm macros and the asm code in the bl31 entrypoint necessary for the instrumentation to AArch32. Since smc dispatch is handled by the bl32 payload on AArch32, we provide this service only if AARCH32_SP=sp_min is set. Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Id33b7e9762ae86a4f4b40d7f1b37a90e5130c8ac
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Bence Szépkúti authored
Switching execution states is only possible if EL3 is AArch64. As such there is no need to validate the entrypoint on AArch32 builds. Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: I3c1eb25b5df296a492870641d274bf65213c6608
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Simon South authored
Enable the workaround for Cortex-A53 erratum 855873 for the Rockchip RK3328, silencing a warning at startup. Change-Id: I5aa29d674d23c096c599abcb5e7dac970f9607d8 Signed-off-by: Simon South <simon@simonsouth.net>
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Hadi Asyrafi authored
Fix FPGA reconfiguration driver logic Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0299c1a71f3456e9b441340314662494b8d3e4a0
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Hadi Asyrafi authored
Mailbox driver now handles variable response length Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic96854fdaadaf48379c5de688392df974e1c99c3
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Hadi Asyrafi authored
Modify mailbox config return code to improve debugging. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0a223291f4c5296203b3295a679a5857a446c692
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Hadi Asyrafi authored
Fix mailbox driver urgent command handling, doorbell routine, and logic optimization. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: If536a383f449ca2a68d60274303ec24f92411505
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Tien Hock, Loh authored
Fixes the SiP Service driver that is responsible for FPGA reconfiguration. Also change the base address of FPGA reconfiguration to 0x400000. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I2b84c12c85cd5fc235247131fec4916ed2fb56c8
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Tien Hock, Loh authored
There are a few issues in mailbox that needs to be fixed. - Send doorbell after an indirect cmd - Do not ring doorbell when polling mailbox response as it should've been sent by send_cmd - remove unneeded cmd_free_offset check - Fix mailbox initialization - Fix get_config_status returning a wrong status when the status is busy - Add command length in mailbox command header Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: If613e2ca889a540a616c62d69ad0086a7cd46536
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Heiko Stuebner authored
Transfering the regions of ddr memory to additionally protect is very much specific to some rockchip internal first stage bootloader and doesn't get used in either mainline uboot or even Rockchip's published vendor uboot sources. This results in a big error ERROR: over or zero region, nr=0, max=10 getting emitted on every boot for most users and such a message coming from early firmware might actually confuse developers working with the system. As this mechanism seems to be only be used by Rockchip's internal miniloader hide it behind a build conditional, so it doesn't confuse people too much. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: I52c02decc60fd431ea78c7486cad5bac82bdbfbe
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Heiko Stuebner authored
So far the px30-related ddr security was loading data for regions to secure from a pre-specified memory location and also setting region0 to secure the first megabyte of memory in hard-coded setting (top=0, end=0, meaning 1MB). To make things more explicit and easier to read add a function doing the settings for specified memory areas, like other socs have and also add an assert to make sure any descriptor read from memory does not overlap the TZRAM security in region0 and TEE security in region1. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: I78441875112bf66a62fde5f1789f4e52a78ef95f
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Heiko Stuebner authored
Similar to others like rk3399 and rk3288 move the secure init to a separate file to unclutter the soc init a bit. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: Iebb38e24f1c7fe5353f139c896fb8ca769bf9691
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Hadi Asyrafi authored
Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I16118d791399f652b6d1093c10092935a3449c32
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Hadi Asyrafi authored
Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use of On-Chip RAM for BL31 specific variables filling down from handoff offset to reduce fragmentation Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099
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Hadi Asyrafi authored
This patch will provide an entrypoint for uboot's spl into BL31. BL31 will also handle secondary cpu state during uboot's cold boot Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3
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