1. 22 Jun, 2017 1 commit
    • Dimitris Papastamos's avatar
      aarch32: Apply workaround for errata 813419 of Cortex-A57 · 6f512a3d
      Dimitris Papastamos authored
      
      
      TLBI instructions for monitor mode won't have the desired effect under
      specific circumstances in Cortex-A57 r0p0. The workaround is to
      execute DSB and TLBI twice each time.
      
      Even though this errata is only needed in r0p0, the current errata
      framework is not prepared to apply run-time workarounds. The current one
      is always applied if compiled in, regardless of the CPU or its revision.
      
      The `DSB` instruction used when initializing the translation tables has
      been changed to `DSB ISH` as an optimization and to be consistent with
      the barriers used for the workaround.
      
      NOTE: This workaround is present in AArch64 TF and already enabled by
      default on Juno.
      
      Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa
      Signed-off-by: default avatarDimitris Papastamos <dimitris.papastamos@arm.com>
      6f512a3d
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