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The CPU Complex (CCPLEX) Power Manager (Denver MCE, or DMCE) is an
offload engine for BPMP to do voltage related sequencing and for
hardware requests to be handled in a better latency than BPMP-firmware.

There are two interfaces to the MCEs - Abstract Request Interface (ARI)
and the traditional NVGINDEX/NVGDATA interface.

MCE supports various commands which can be used by CPUs - ARM as well
as Denver, for power management and reset functionality. Since the
linux kernel is the master for all these scenarios, each MCE command
can be issued by a corresponding SMC. These SMCs have been moved to
SiP SMC space as they are specific to the Tegra186 SoC.

Change-Id: I67bee83d2289a8ab63bc5556e5744e5043803e51
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186 is the newest SoC in the Tegra family which consists
of two CPU clusters - Denver and A57. The Denver cluster hosts
two next gen Denver15 CPUs while the A57 cluster hosts four ARM
Cortex-A57 CPUs. Unlike previous Tegra generations, all the six
cores on this SoC would be available to the system at the same
time and individual clusters can be powered down to conserve
power.

Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e
Signed-off-by: Wayne Lin <wlin@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds driver for the Memory Controller (v2) in the newer
Tegra SoCs. The newer hardware uses ARM's SMMU hardware instead of
the proprietary block in the past.

Change-Id: I78359da780dc840213b6e99954e45e34428d4fff
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch opens up the interfaces to read the chip's major/minor versions
for all Tegra drivers to use.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The NVidia Tegra 210 SoC contains Cortex-A53 CPUs which are affected by
erratum 855873.

Enable the workaround that TF provides to fix this erratum.

Change-Id: I6cef4ac60ae745e9ce299ee22c93b9d2c4f6c5f2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

This patch enables the following erratas for the Tegra210 SoC:

* Cortex-A57
=============
- A57_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A57_826974
- ERRATA_A57_826977
- ERRATA_A57_828024
- ERRATA_A57_829520
- ERRATA_A57_833471

* Cortex-A53
=============
- A53_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A53_826319
- ERRATA_A53_836870

Tegra210 uses Cortex-A57 revision: r1p1 and Cortex-A53 revision: r0p2.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch enables the SEPARATE_CODE_AND_RODATA build flag for all
Tegra platforms, to allow setting proper MMU attributes for the RO
data and the code.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The linux kernel v3.10 does not use System Suspend function ID, whereas
v4.4 uses it. This means affinity levels 0/1 will have different state id
values during System Suspend entry. This patch updates the assert criteria
to check both the state id values.

Change-Id: I07fcaf99501cc9622e40d0a2c1eb4a4a160be10a
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch allows the NS world to pass 64-bit base address for
the Video Memory carveout region.

Change-Id: I7e47cc1f5425bd39c6763755b801517013e1e0cd
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch increases the ADDR_SPACE_SIZE macro (virtual address)
to 35 bits, to support max memory of 32G, for all Tegra platforms.

Change-Id: I8e6861601d3a667d7428988c7596b0adebfa0548
Signed-off-by: Steven kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Some platforms might want to keep the uart console disabled
during boot. This patch checks if the platform supports a
console, before calling console_init().

Change-Id: Icc9c59cb979d91fd0a72e4732403b3284bdd2dfc
Signed-off-by: Damon Duan <danield@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch modifies the TZDRAM base address to the new aperture
allocated by the bootloader.

Change-Id: Id158d15b1ec9aa681136d258e90fbba930aebf92
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch sets the core power state during cluster power down,
so that the 'get_target_pwr_state' handler can calculate the
proper states for all the affinity levels.

Change-Id: If4adb001011208916427ee1623c6c923bed99985
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch fixes the 'tegra_soc_get_target_pwr_state' handler used to
calculate the proper state for each of the affinity levels.

Change-Id: Id16bd15b96f0fc633ffeac2d7a390592fbd0454b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch uses GICD_BASE to calculate the GICD_ISPENDR regsiter address
in the platform's 'plat_crash_print_regs' routine.

Reported by: Seth Eatinger <seatinger@nvidia.com>

Change-Id: Ic7be29abc781f475ad25b59582ae60a0a2497377
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch removes the console_init() from runtime_setup() as we already
initialize it earlier and disables/enables it across "System Suspend".

Change-Id: I992d3ca56ff4797faf83e8d7fa52c0ef3e1c3367
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds support to identify the underlying platform
on which we are running. The currently supported platforms
are actual silicon and simulation platforms.

Change-Id: Iadf96e79ec663b3dbd1a18e9bb95ffcdb82fc8af
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch implements a per-soc handler to calculate the target
power state for the cluster/system. A weak implementation of the
handler is provided for platforms to use by default.

For SoCs with multiple CPU clusters, this handler would provide
the individual cluster/system state, allowing the PSCI service to
flush caches during cluster/system power down.

Change-Id: I568cdb42204f9841a8430bd9105bd694f71cf91d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds support to relocate the BL32 image from the NS
memory to TZDRAM during cold boot. The NS memory buffer is
cleared out after the process completes.

Change-Id: I1a033ffe73b8c309449f874d5187708d0a8846d2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch implements handlers which platforms can override to
get the BL31 arguments passed by the previous bootloader.

Change-Id: I6b9628a984644ce1b5de5aa6d7cd890e57241d89
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch returns pointer to the BL32 entrypoint info only if
it is valid.

Change-Id: I71ce3c4626681753c94f3a7bbaa50c26c74874cb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch configures the TZDRAM fence during early platform
setup to allow the memory controller to enable DRAM encryption
before the TZDRAM actually gets used.

Change-Id: I0169ef9dda75699527b4e30c9e617a9036ba1d76
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch restores the TZRAM fence and the access permissions
on exiting the "System Suspend" state.

Change-Id: Ie313fca5a861c73f80df9639b01115780fb6e217
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch enables L2 ECC and Parity Protection for ARM Cortex-A57 CPUs
for Tegra SoCs.

Change-Id: I038fcd529991d0201a4951ce2730ab71b1c980f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch modifies the secure IRQ registration process to allow platforms
to specify the target CPUs as well as the owner of the IRQ. IRQs "owned"
by the EL3 would return INTR_TYPE_EL3 whereas those owned by the Trusted
OS would return INTR_TYPE_S_EL1 as a result.

Change-Id: I528f7c8220d0ae0c0f354e78d69e188abb666ef6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.

The NS world driver issues an SMC initially to register it's
handler. The monitor firmware stores this handler address and
jumps to it when the FIQ interrupt fires. Upon entry into the
NS world the driver then issues another SMC to get the CPU
context when the FIQ fired. This allows the NS world driver to
determine the CPU state and call stack when the interrupt
fired. Generally, systems register watchdog interrupts as FIQs
which are then used to get the CPU state during hangs/crashes.

Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra chips support multiple FIQ interrupt sources. These interrupts
are enabled in the GICD/GICC interfaces by the tegra_gic driver. A
new FIQ handler would be added in a subsequent change which can be
registered by the platform code.

This patch adds the GIC programming as part of the tegra_gic_setup()
which now takes an array of all the FIQ interrupts to be enabled for
the platform. The Tegra132 and Tegra210 platforms right now do not
register for any FIQ interrupts themselves, but will definitely use
this support in the future.

Change-Id: I0ea164be901cd6681167028fea0567399f18d4b8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds a platform handler to calculate the proper target power
level at the specified affinity level.

Tegra platforms assign a local state value in order of decreasing depth
of the power state i.e. for two power states X & Y, if X < Y then X
represents a shallower power state than Y. As a result, the coordinated
target local power state for a power domain will be the maximum of the
requested local power state values.

Change-Id: I67360684b7f5b783fcfdd605b96da5375fa05417
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch includes platform_def.h required to access UART macros -
"TEGRA_BOOT_UART_CLK_IN_HZ" and "TEGRA_CONSOLE_BAUDRATE" from
tegra_helpers.S.

Change-Id: Ieb63968a48dc299d03e81ddeb1ccc871cf3397a1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch removes the restriction of allowing SiP calls only from the
non-secure world. The secure world can issue SiP calls as a result of
this patch now.

Change-Id: Idd64e893ae8e114bba0196872d3ec544cac150bf
Signed-off-by: Wayne Lin <wlin@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds a weak handler for early platform setup which
can be overriden by the soc-specific handlers to perform any
early setup tasks.

Change-Id: I1a7a98d59b2332a3030c6dca5a9b7be977177326
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds support to relocate BL3-1 code to BL31_BASE in case
we cold boot to a different address. This is particularly useful to
maintain compatibility with legacy BL2 code.

This patch also checks to see if the image base address matches either
the TZDRAM or TZSRAM base.

Change-Id: I72c96d7f89076701a6ac2537d4c06565c54dab9c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This change disables the cache non-temporal hints for A57 and
A53 CPUs on Tegra.

Change-Id: I279d95aec5afbc3ca3cc4b34aa16de3f2c83a4fc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds the pwr_domain_power_down_wfi() handler for Tegra
platforms which in turn executes the soc specific `power_down_wfi`
handler.

Change-Id: I5deecc09959db3c3d73f928f5c871966331cfd95
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch maps the TZDRAM carveout used by the BL31. In the near
future BL31 would be running from the TZRAM for security and
performance reasons. The only downside to this solution is that
the TZRAM loses its state in System Suspend. So, we map the TZDRAM
carveout that the BL31 would use to save its state before entering
System Suspend.

Change-Id: Id5bda7e9864afd270cf86418c703fa61c2cb095f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch increases the BL31 image size for all Tegra platforms to
256KB, so that we can relocate BL31 to TZSRAM on supported chips.

Change-Id: I467063c68632b53b5d4ef8ff1f76f5988096bd9c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch uses the Memory controller driver's handler to restore
its settings and moves the other chip specific code to their own
'pwr_domain_on_finish' handlers.

Change-Id: I3c9d23bdab9e2e3c05034ff6812cf941ccd7a75e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch moves the code to disable DCO operations out from common
CPU files. This allows the platform code to call thsi API as and
when required. There are certain CPU power down states which require
the DCO to be kept ON and platforms can decide selectively now.

Change-Id: Icb946fe2545a7d8c5903c420d1ee169c4921a2d1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch enables the PSCI_EXTENDED_STATE_ID macro. Tegra platforms
have moved on to using the extended state ID for CPU_SUSPEND, where
the NS world passes the state ID and wakeup time as part of the
state ID field.

Change-Id: Ie8b0fec285d8b2330bc26ff239a4f628425c9fcf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The platform power states, PLAT_MAX_RET_STATE and PLAT_MAX_OFF_STATE,
can change on Tegra SoCs and so should be defined per-soc.

This patch moves these macro definitions to individual SoC's tegra_def.h
files.

Change-Id: Ib9b2752bc4d79cef6f79bee49882d340f71977a2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>