1. 03 Oct, 2018 1 commit
  2. 28 Sep, 2018 4 commits
  3. 03 Sep, 2018 1 commit
  4. 30 Aug, 2018 7 commits
  5. 13 Aug, 2018 1 commit
  6. 30 Jul, 2018 1 commit
  7. 26 Jul, 2018 1 commit
  8. 19 Jul, 2018 1 commit
    • Roberto Vargas's avatar
      cci: Wait before reading status register · ae551a13
      Roberto Vargas authored
      
      
      The functions cci_enable_snoop_dvm_reqs and cci_disable_snoop_dvm_reqs write
      in the SNOOP_CTRL_REGISTER of the slave interface and it polls the status
      register to be sure that the operation is finished before leaving the
      functions. If the write in SNOOP_CTRL_REGISTER is reordered after the first
      read in the status register then these functions can finish before
      enabling/disabling snoops and DVM messages.
      
      The CCI500 TRM specifies:
      
      	Wait for the completion of the write to the Snoop Control Register
      	before testing the change_pending bit.
      
      Change-Id: Idc7685963f412be1c16bcd3c6e3cca826e2fdf38
      Signed-off-by: default avatarRoberto Vargas <roberto.vargas@arm.com>
      ae551a13
  9. 12 Jun, 2018 2 commits
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.3 Part 2 · 896a5902
      Daniel Boulby authored
      
      
      Use a _ prefix for Macro arguments to prevent that argument from
      hiding variables of the same name in the outer scope
      
      Rule 5.3: An identifier declared in an inner scope shall not
                hide an identifier declared in an outer scope
      
      Fixed For:
          make LOG_LEVEL=50 PLAT=fvp
      
      Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708
      Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      896a5902
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.1 · 87d3aacc
      Daniel Boulby authored
      
      
      Rule 5.1: External identifiers shall be distinct
      
      Some of the identifier names in the GICv3 driver were so long that the
      first 31 characters were identical. This patch shortens these names to
      make sure they are different.
      
      Fixed for:
          LOG_LEVEL=50 PLAT=fvp
      
      Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90
      Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      87d3aacc
  10. 27 Apr, 2018 1 commit
  11. 09 Apr, 2018 1 commit
  12. 03 Apr, 2018 2 commits
    • Andre Przywara's avatar
      gicv3: Fix support for systems without secure interrupts · 205cf6e7
      Andre Przywara authored
      
      
      Accessing the interrupt_props array only happens inside a loop over
      interrupt_props_num, so the GICv3 driver can cope with no secure
      interrupts. This allows us to relax the asserts that insists on
      a non-NULL interrupt_props pointer and at least one secure interrupt.
      This enables GICv3 platforms which have no need for a secure interrupt.
      
      This only covers the non-deprecated code paths.
      
      Change-Id: I49db291906512f56af065772f69acb281dfbdcfb
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      205cf6e7
    • Samuel Holland's avatar
      gicv2: Fix support for systems without secure interrupts · 9d6d800d
      Samuel Holland authored
      
      
      Accessing the interrupt_props array only happens inside a loop over
      interrupt_props_num, so the GICv2 driver can cope with no secure
      interrupts. As in fact we have already some asserts in place that
      respect that, lets change the final place where we insist on a non-NULL
      pointer to relax that.
      This enables GICv2 platforms which have no need for a secure interrupt.
      
      This only covers the non-deprecated code paths.
      
      Also we remove a now redundant assert().
      
      Change-Id: Id100ea978643d8558335ad28649d55743fe9bd4c
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      9d6d800d
  13. 26 Mar, 2018 2 commits
  14. 05 Mar, 2018 1 commit
  15. 01 Mar, 2018 1 commit
    • Dan Handley's avatar
      Emit warnings when using deprecated GIC init · dcf01a0a
      Dan Handley authored
      
      
      Emit runtime warnings when intializing the GIC drivers using the
      deprecated method of defining integer interrupt arrays in the GIC driver
      data structures; interrupt_prop_t arrays should be used instead. This
      helps platforms detect that they have migration work to do. Previously,
      no warning was emitted in this case. This affects both the GICv2 and GICv3
      drivers.
      
      Also use the __deprecated attribute to emit a build time warning if these
      deprecated fields are used. These warnings are suppressed in the GIC
      driver compatibility functions but will be visible if platforms use them.
      
      Change-Id: I6b6b8f6c3b4920c448b6dcb82fc18442cfdf6c7a
      Signed-off-by: default avatarDan Handley <dan.handley@arm.com>
      dcf01a0a
  16. 28 Feb, 2018 2 commits
  17. 21 Feb, 2018 1 commit
  18. 14 Feb, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Remove URLs from comments · fb1198b1
      Antonio Nino Diaz authored
      
      
      This fixes all defects according to MISRA Rule 3.1: "The character
      sequences /* and // shall not be used within a comment". This affects
      all URLs in comments, so they have been removed:
      
      - The link in `sdei_state.c` can also be found in the documentation file
        `docs/sdei.rst`.
      
      - The bug that the file `io_fip.c` talks about doesn't affect the
        currently supported version of GCC, so it doesn't make sense to keep
        the comment. Note that the version of GCC officially supported is the
        one that comes with Linaro Release 17.10, which is GCC 6.2.
      
      - The link in `tzc400.c` was broken, and it didn't correctly direct to
        the Technical Reference Manual it should. The link has been replaced
        by the title of the document, which is more convenient when looking
        for the document.
      
      Change-Id: I89f60c25f635fd4c008a5d3a14028f814c147bbe
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      fb1198b1
  19. 24 Jan, 2018 1 commit
  20. 19 Jan, 2018 1 commit
  21. 13 Nov, 2017 2 commits
    • Jeenu Viswambharan's avatar
      GIC: Fix Group 0 enabling · 385f1dbb
      Jeenu Viswambharan authored
      
      
      At present, the GIC drivers enable Group 0 interrupts only if there are
      Secure SPIs listed in the interrupt properties/list. This means that,
      even if there are Group 0 SGIs/PPIs configured, the group remained
      disabled in the absence of a Group 0 SPI.
      
      Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when
      corresponding SGIs/PPIs are present.
      
      Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      385f1dbb
    • Jeenu Viswambharan's avatar
      GICv2: Fix populating PE target data · 058efeef
      Jeenu Viswambharan authored
      
      
      This patch brings in the following fixes:
      
        - The per-PE target data initialized during power up needs to be
          flushed so as to be visible to other PEs.
      
        - Setup per-PE target data for the primary PE as well. At present,
          this was only setup for secondary PEs when they were powered on.
      
      Change-Id: Ibe3a57c14864e37b2326dd7ab321a5c7bf80e8af
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      058efeef
  22. 08 Nov, 2017 1 commit
    • Etienne Carriere's avatar
      ARMv7: GICv2 driver can manage GICv1 with security extension · 64deed19
      Etienne Carriere authored
      
      
      Some SoCs integrate a GIC in version 1 that is currently not supported
      by the trusted firmware. This change hijacks GICv2 driver to handle the
      GICv1 as GICv1 is compatible enough with GICv2 as far as the platform
      does not attempt to play with virtualization support or some GICv2
      specific power features.
      
      Note that current trusted firmware does not use these GICv2 features
      that are not available in GICv1 Security Extension.
      
      Change-Id: Ic2cb3055f1319a83455571d6d918661da583f179
      Signed-off-by: default avatarEtienne Carriere <etienne.carriere@linaro.org>
      64deed19
  23. 16 Oct, 2017 4 commits
    • Jeenu Viswambharan's avatar
      GIC: Allow specifying interrupt properties · c639e8eb
      Jeenu Viswambharan authored
      
      
      The GIC driver initialization currently allows an array of interrupts to
      be configured as secure. Future use cases would require more interrupt
      configuration other than just security, such as priority.
      
      This patch introduces a new interrupt property array as part of both
      GICv2 and GICv3 driver data. The platform can populate the array with
      interrupt numbers and respective properties. The corresponding driver
      initialization iterates through the array, and applies interrupt
      configuration as required.
      
      This capability, and the current way of supplying array (or arrays, in
      case of GICv3) of secure interrupts, are however mutually exclusive.
      Henceforth, the platform should supply either:
      
        - A list of interrupts to be mapped as secure (the current way).
          Platforms that do this will continue working as they were. With this
          patch, this scheme is deprecated.
      
        - A list of interrupt properties (properties include interrupt group).
          Individual interrupt properties are specified via. descriptors of
          type 'interrupt_prop_desc_t', which can be populated with the macro
          INTR_PROP_DESC().
      
      A run time assert checks that the platform doesn't specify both.
      
      Henceforth the old scheme of providing list of secure interrupts is
      deprecated. When built with ERROR_DEPRECATED=1, GIC drivers will require
      that the interrupt properties are supplied instead of an array of secure
      interrupts.
      
      Add a section to firmware design about configuring secure interrupts.
      
      Fixes ARM-software/tf-issues#262
      
      Change-Id: I8eec29e72eb69dbb6bce77879febf32c95376942
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      c639e8eb
    • Jeenu Viswambharan's avatar
      GIC: Add helpers to set interrupt configuration · 22966106
      Jeenu Viswambharan authored
      
      
      The helpers perform read-modify-write on GIC*_ICFGR registers, but don't
      serialise callers. Any serialisation must be taken care of by the
      callers.
      
      Change-Id: I71995f82ff2c7f70d37af0ede30d6ee18682fd3f
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      22966106
    • Jeenu Viswambharan's avatar
      GIC: Add API to set priority mask · d55a4450
      Jeenu Viswambharan authored
      
      
      API documentation updated.
      
      Change-Id: I40feec1fe67a960d035061b54dd55610bc34ce1d
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      d55a4450
    • Jeenu Viswambharan's avatar
      GIC: Add API to set/clear interrupt pending · a2816a16
      Jeenu Viswambharan authored
      
      
      API documentation updated.
      
      Change-Id: I14e33cfc7dfa93257c82d76fae186b17a1b6d266
      Co-authored-by: default avatarYousuf A <yousuf.sait@arm.com>
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      a2816a16