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The Memory controller expects the TZDRAM base value at 1MB granularity
and the current driver does not respect that limitation. This patch
fixes that anomaly.

Change-Id: I6b72270f331ba5081e19811df4a78623e457341a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

In order to make sure SMC call is within 25us, this patch reduces number of RAS
errors accessed to 8 at most for each SMC call and takes a input/output
parameter to specify in progress RAS error record index.

The measured SMC call latency is about 20us under Linux test kernel driver.

Change-Id: Ia1b57c8673e0193dc341a36af0b5c09fb48f965f
Signed-off-by: David Pu <dpu@nvidia.com>

The TEGRA_GICv2_SOURCES contains the list of GIC sources required
to compile the GICv2 support for platforms.

This patch includes the TEGRA_GICv2_SOURCES macro from individual
makefiles to allow future platforms to use suport for GICv3.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I429b1a0c7764ab370675f873a50cecda871110cb

This patch adds memory barriers to the trampoline code copying TZDRAM
contents to SysRAM during exit from System Suspend. These barriers
make sure that all the copies go through before we start executing in
SysRAM.

Reported by: Nathan Tuck <ntuck@nvidia.com>

Change-Id: I3fd2964086b6c0e044cc4165051a4801440db9cd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which will be reflected by
this register.

This patch reads the control register before processing
a video memory resize request. An error code, -ENOTSUP,
is returned if the feature is locked.

Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

MMIO writes should verify that the writes actually went through.
Read the value back after the write operation, perform assert
if the read back value is not same as the write value.

Change-Id: Id2ceb014116f3aa6a9e86505ca1ae9911470a679
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

This patch removes the unused cortex_a53.h header file from
common Tegra files.

This change fixes the violation of CERTC Rule: DCL23.

Change-Id: Iaf7c34cc6323b78028258e188c00724c52afba85
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

During boot the platform enables dual execution for Xavier CPUs.
This patch reads back the ACTLR_ELx register to verify that the bit
is actually set. It asserts if the bit is not set.

Change-Id: I5ba9491ced86285d307b95efa647a427ff77c79e
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

The firewall settings for the hardware resources are present in the
Security Configuration Registers. The firewall settings are programmed
by other software components and so must be verified for correctness
before touching the hardware resources they protect.

This patch reads the firewall settings during early boot and asserts
if the settings mismatch.

Change-Id: I53cc9aeadad32e54e460db0fa2c38e46bcc92066
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

* changes:
  qti/sc7180: Do shutdown handling outside qtiseclib
  qti: Add SPMI PMIC arbitrator driver
  qti/sc7180: Fix GIC-600 support setting

The current implementation of snprintf() does not support pointer and
hexadecimal format specifiers, which can be needed, for instance, for
DTB manipulations.

This patch adds that functionality by borrowing some code from the
printf() implementation.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I2076ea46693a73a04890982bf20e3c633c2767fb

With an open source SPMI driver we can now remove qtiseclib involvement
in reset and shutdown handling by setting the required registers
directly.

Change-Id: I6bf1db15734048df583daa2a4ee98701c6ece621
Signed-off-by: Julius Werner <jwerner@chromium.org>

* changes:
  Tegra194: introduce support for `SPD=spmd`
  Tegra: introduce backend support to compile libfdt
  Tegra: disable signed comparison
  plat: common: include "bl_common.h" from plat_spmd_manifest.c

* changes:
  Tegra194: remove AON_WDT IRQ mapping
  Tegra: smmu: add smmu_verify function
  Tegra: TZDRAM setup from soc specific early_boot handlers
  Tegra: remove "platform_get_core_pos" function
  Tegra: print GICC registers conditionally
  lib: cpus: sanity check pointers before use
  Tegra: spe: do not flush console in console_putc
  Tegra: verify platform compatibility

This patch adds a very rudimentary driver for the SPMI arbitrator used
to access the PMIC. It doesn't support all the controller's actual
arbitration features, so it should probably not be used concurrently
with a running kernel (and it's also not optimized for performance). But
it can be used to set a few registers during boot or on shutdown to
control reset handling, which is all we need it for.

Change-Id: I8631c34a2a89ac71aa1ec9b8266e818c922fe34a
Signed-off-by: Julius Werner <jwerner@chromium.org>

The patch adding platform support for sc7180 landed around roughly the
same time as the patch that changed GICV3_IMPL to GICV3_SUPPORT_GIC600.
Thus the sc7180 Makefile is still using the old variable name which now
no longer does anything, and it hangs on boot due to the lacking GIC-600
support. This patch fixes the issue.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id76ada1445c3c5ac9a5a3697b4e749088b89d796

This patch introduces the following changes to enable
compilation for `SPD=spmd` command line option.

* compile plat_spmd_manifest.c
* compile libfdt source files

Verified with the `SPD=spmd` command line option for
Tegra194 platforms.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I7f57aa4f1756b19f78d87415bb80794417174bc8

This patch includes the following files from libc to
compile libfdt:

* memchr.c
* memcmp.c
* strrchr.c

The BUILD_PLAT macro is evaluated earlier to allow libfdt
installation to the right directory.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ie43fcf701dc051670e6372e21b3a84a6416c1735

libfdt does not support the -Wsign-compare compiler option
and the right patch will eventually be pushed upstream.

This patch disables the -Wsign-compare compiler option
to allow libfdt compilation for Tegra platforms until
the actual issue is fixed.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ib7a93946cad1ea9ec1b46751edb79a74c08ed0ac

This patch includes the bl_common.h from plat_spmd_manifest.c to
fix the following compilation errors

<snip>
plat/common/plat_spmd_manifest.c: In function 'plat_spm_core_manifest_load':
plat/common/plat_spmd_manifest.c:130:18: error: implicit declaration of function 'page_align' [-Werror=implicit-function-declaration]
  130 |  pm_base_align = page_align(pm_base, UP);
      |                  ^~~~~~~~~~
plat/common/plat_spmd_manifest.c:130:38: error: 'UP' undeclared (first use in this function); did you mean 'UL'?
  130 |  pm_base_align = page_align(pm_base, UP);
      |                                      ^~
      |                                      UL
plat/common/plat_spmd_manifest.c:130:38: note: each undeclared identifier is reported only once for each function it appears in
plat/common/plat_spmd_manifest.c:146:38: error: 'DOWN' undeclared (first use in this function)
  146 |  pm_base_align = page_align(pm_base, DOWN);
      |                                      ^~~~
cc1: all warnings being treated as errors
<snip>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ib8edb36c6a80a23df2462e708c513c966aab1fef

This patch removes the unused interrupt mapping for AON_WDT
for all Tegra194 platforms.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I475a1e83f809c740e62464b5b4e93cb0a2e33d6b

The SMMU configuration can get corrupted or updated by
external clients during boot without our knowledge.

This patch introduces a "verify" function for the SMMU
driver, to check that the boot configuration settings are
intact.  Usually, this function should be called at the
end of the boot cycle.

This function only calls panic() on silicon platforms.

Change-Id: I2ab45a7f228781e71c73ba1f4ffc49353effe146
Signed-off-by: George Bauernschmidt <georgeb@nvidia.com>

TZDRAM setup is not required for all Tegra SoCs. The previous bootloader
can enable the TZDRAM fence due to architectural improvements in the
newer chips.

This patch moves the TZDRAM setup to early_boot handlers for SoCs to
handle this scenario.

Change-Id: I6481b4f848a4dadc20cb83852cd8e19a242b3a34
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch removes the deprecated 'plat_core_pos_by_mpidr' function
from the Tegra platform port.

Change-Id: I32e06cb7269e4fbfaf9ad6c26d0722201f982f9e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The GICC interface exists only on the interrupt controllers following
the GICv2 specification.

This patch prints the GICC register contents from the platform's macro,
plat_crash_print_regs' only when TEGRA_GICC_BASE is defined. This
allows platforms using future versions of the GIC specification to
still use this macro.

Change-Id: Ia5762d0a1ae28c832664d69362a7776e46a22ad1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The cpu_ops structure contains a lot of function pointers. It
is a good idea to verify that the function pointer is not NULL
before executing it.

This patch sanity checks each pointer before use to prevent any
unforeseen crashes. These checks have been enabled for debug
builds only.

Change-Id: Ib208331c20e60f0c7c582a20eb3d8cc40fb99d21
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

SPE no longer requires the flush bit to be set to start transmitting
characters over the physical uart. Therefore, the flush bit is no
longer required when calling console_core_putc. However, flushing the
console still requires the flush bit.

This patch removes the flush bit from the mailbox messages in
console_core_putc to improve ACK latency.

Original change by: Mustafa Bilgen <mbilgen@nvidia.com>

Change-Id: I5b7d1f3ea69ea2ce308566dbaae222b04e4c373d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch verifies that the binary image is compatible with
chip ID of the platform.

Change-Id: I28db221b4442aa8827a092faadf32f110d7c5cb4
Signed-off-by: kalyanic <kalyanic@nvidia.com>

Allocated 512-959 SPI numbers for remote n1sdp chip and same has been
referenced for GIC routing table.

Change-Id: Id79ea493fd665ed93fe9644a59e363ec10441098
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>

Currently, the tool's makefile override the tool's binary name
which is already been defined in the main makefile.
Hence fix is provided so that the tool's makefile get the tool's
binary name from the main makefile instead of overriding it.

Change-Id: I8af2bd391a96bba2dbcddef711338a94ebf5f038
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

This reverts commit e7d344de.
 This reverts the patch https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5313 due to a timing issue with the merge.  The merge occurred at the same time as the additional comments and thusly were were not seen until the merge was done.  This reverts the change and additional patches from Alexei will follow to address the concerns expressed in the orignal patch.

Change-Id: Iae5f6403c93ac13ceeda29463883fcd4c437f2b7

Signed-off-by: Ruari Phipps <ruari.phipps@arm.com>
Change-Id: I4e9fbfcfda4ed4b87d5ece1c609c57c73d617d4c

* changes:
  SPMC: embed secondary core ep info into to SPMC context
  SPMC: manifest changes to support multicore boot
  SPMD: secondary cores PM on and off SPD hooks relayed to SPMC
  SPMD: handle SPMC message to register secondary core entry point
  SPMD: introduce SPMC to SPMD messages
  SPMD: register the SPD PM hooks
  SPMD: add generic SPD PM handlers
  SPMD: enhance SPMC internal boot states
  SPMD: entry point info get helper

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Icdb15b8664fb3467ffd55b44d1f0660457192586