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Change-Id: Ia120bcaacea3a462ab78db13f84ed23493033601
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>

* changes:
  Tegra194: remove L2 ECC parity protection setting
  Tegra194: sip_calls: mark unused parameter as const
  Tegra194: implement handler to retrieve power domain tree
  Tegra194: mce: fix function declaration conflicts
  Tegra194: add macros to read GPU reset status
  Tegra194: skip notifying MCE in fake system suspend
  Tegra194: Enable system suspend

* changes:
  DOC: Update ROMLIB page with memory impact info
  ROMLIB: Optimize memory layout when ROMLIB is used

Complete the Library at ROM documentation with information regarding
the memory impact of the feature.

Change-Id: I5a10620a8e94f123021bb19523a36d558b330deb
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

ROMLIB extract functions code from BL images to put them inside ROM.
This has for effect to reduce the size of the BL images.

This patch take this size reduction into consideration to optimize the
memory layout of BL2.
A new "PLAT_ARM_BL2_ROMLIB_OPTIMIZATION" macro is defined and used to
reduce "PLAT_ARM_MAX_BL2_SIZE". This allows to remove the gap between
BL1 and BL2 when ROMLIB is used and provides more room for BL31.

The current memory gain is 0x6000 for fvp and 0x8000 for juno.

Change-Id: I71c2c2c63b57bce5b22a125efaefc486ff3e87be
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

The number of levels in the topology has not changed but the count of
processing elements on the lowest layer is now multiplied by the value
of FVP_MAX_PE_PER_CPU.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: Ia1568a40ea33dbbbcdfab6c8ab6d19f4db0b8eb4

Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Section 3.6.1 in the GIC-600 TRM describes
the power-up and power-down sequence in pseudo code,
which deviates from the current TF-A implementation
in drivers/arm/gic/v3/gic600.c.
For powering on a redistributor, the pseudo code suggests
to loop over the whole sequence (check for transition,
write request bit) instead of just looping over the
ready bit read as TF-A does in gic600_pwr_on().
This patch fixes GIC-600 power up sequence according
to the TRM.

Change-Id: I445c480e96ba356b69a2d8e5308ffe6c0a97f45b
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Change-Id: Ibca94eae1a9a89c98b4d7cb5b4fd8943bf854030
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Previous implementation of timers assumed that clk_div has pretty
representation in MHz (10MHz, 100MHz, etc). Unusual frequencies
(99.99MHz) were causing assertion error and made udelay unusable.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ic915fff224369d113fd9f8edbcfff169fca8beac

The pre-processor directives make it hard to read the non-TBB version of
this function. Refactor the code to improve readability. No functional
change introduced.

In particular, introduce a new helper function load_image_flush(),
that simply loads an image and flushes it out to main memory. This is
the only thing load_auth_image_internal() needs to do when TBB is
disabled or when authentication is dynamically disabled.

In other cases, we need to recursively authenticate the parent images up
to the root of trust. To make this clearer, this code gets moved to a
TBB-specific helper function called load_auth_image_recursive().

As a result, load_auth_image_internal() now boils down to calling the
right helper function (depending on TBB enablement and dynamic
authentication status).

Change-Id: I20a39a3b833810b97ecf4219358e7d2cac263890
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

This patch removes the code to enable L2 ECC parity protection
bit, as Tegra194 does not have any Cortex-A57 CPUs.

Change-Id: I4b56595fea2652e8bb8ab4a7ae7567278ecff9af
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

This patch marks the unused parameter 'cookie', to the
plat_sip_handler() function, as const to fix an issue
flagged by the MISRA scan.

Change-Id: I53fdd2caadf43fef17fbc3a50a18bf7fdbd42d39
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch implements the platform handler to return the pointer
to the power domain tree.

Change-Id: I74ea7002c7a461a028b4a252bbd354256fdc0647
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

To fix MISRA defects, remove union in t186 MCE drivers
this driver should compatible with that.

Change-Id: I09e96a1874dd86626c7e41c92a1484a84e387402
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

This patch adds macros to check the GPU reset status bit, before
resizing the VideoMem region.

Change-Id: I4377c1ce1ac6d3bd14c7db83526b99d72bdb41ed
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

- In pre-silicon platforms, MCE might not be ready
  to support system suspend(SC7)
- Thus, in fake system suspend mode, bypass waiting for
  MCE's acknowledgment to enter system suspend

Change-Id: Ia3c010ce080c4283ab1233ba82e3e577adca34f6
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

This patch does the following:
1. Populate the cstate info corresponding to system suspend
   and communicate it to the MCE
2. Ask for MCE's acknowledgement for entering system suspend
   and instruct MCE to get inside system suspend once
   permitted

Change-Id: I51e1910e24a7e61e36ac2d12ce271290e433e506
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ia1ff13be1308e63c2854d2b6e5f6651750186abe

The new dts file overrides the MPIDR values of the processing elements
which were defined in the common dtsi file. The new dts file defines
four cores in a single cluster, each core having two threads.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I0f8d8d250289077aee11eede4508871bb61dbc88

* changes:
  Tegra194: add macros for security carveout configuration registers
  Tegra194: add 'TEGRA_TMRUS_SIZE' macro
  Tegra194: Fix TEGRA186_SMMU_CTX_SIZE
  Tegra194: Dont run MCE firmware on Emulation
  Tegra194: remove GPU, MPCORE and PTC registers from streamid list
  Tegra194: Support SMC64 encoding for MCE calls
  Tegra194: Enable MCE driver
  Tegra194: enable SMMU
  Tegra194: add support for multiple SMMU devices
  Tegra194: add SMMU and mc_sid support
  Tegra194: psci: support for 64-bit TZDRAM base
  Tegra194: base commit for the platform
  Revert "Tegra: Add support for fake system suspend"

`unsigned long` should be replaced to
1. `unsigned int` or `unsigned long long` - If fixed,
based on the architecture AArch32 or AArch64
2. `u_register_t` - If it is supposed to be 32-bit
wide in AArch32 and 64-bit wide in AArch64.

Translation descriptors are always 32-bit wide, here
`uint32_t` is used to describe the `exact size` of
translation descriptors instead of `unsigned int` which
guarantees minimum 32-bits
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I6a2af2e8b3c71170e2634044e0b887f07a41677e

* changes:
  gic/gic600: add support for multichip configuration
  plat/arm/gicv3: add support for probing multiple GIC Redistributor frames

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link, for now only dual-chip
is supported.

Whether or not multiple chips are present is dynamically probed by
SCP firmware and passed on to TF-A, routing table will be set up
only if multiple chips are present.

Initialize GIC-600 multichip operation by overriding the default GICR
frames with array of GICR frames and setting the chip 0 as routing
table owner.

Change-Id: Ida35672be4bbf4c517469a5b330548d75e593ff2
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

Add support to configure GIC-600's multichip routing table registers.
Introduce a new gic600 multichip structure in order to support platforms
to pass their GIC-600 multichip information such as routing table owner,
SPI blocks ownership.

This driver is currently experimental and the driver api may change in
the future.

Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

Earlier PIE support was enabled for all arm platforms when
RESET_TO_BL31=1, but later on it was restricted only to FVP with patch
SHA d4580d17

 because of n1sdp platform.

Now it has been verified that PIE does work for n1sdp platform also, so
enabling it again for all arm platforms.

Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>