1. 20 Feb, 2014 5 commits
    • Achin Gupta's avatar
      Specify address of UART device to use as a console · 8aa0cd43
      Achin Gupta authored
      This patch adds the ability to specify the base address of a UART
      device for initialising the console. This allows a boot loader stage
      to use a different UART device from UART0 (default) for the console.
      
      Change-Id: Ie60b927389ae26085cfc90d22a564ff83ba62955
      8aa0cd43
    • Achin Gupta's avatar
      Factor out translation table setup in ARM FVP port · a0cd989d
      Achin Gupta authored
      This patch factors out the ARM FVP specific code to create MMU
      translation tables so that it is possible for a boot loader stage to
      create a different set of tables instead of using the default ones.
      The default translation tables are created with the assumption that
      the calling boot loader stage executes out of secure SRAM. This might
      not be true for the BL3_2 stage in the future.
      
      A boot loader stage can define the `fill_xlation_tables()` function as
      per its requirements. It returns a reference to the level 1
      translation table which is used by the common platform code to setup
      the TTBR_EL3.
      
      This patch is a temporary solution before a larger rework of
      translation table creation logic is introduced.
      
      Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6
      a0cd989d
    • Achin Gupta's avatar
      Add support for BL3-2 in BL3-1 · 35ca3511
      Achin Gupta authored
      This patch adds the following support to the BL3-1 stage:
      
      1. BL3-1 allows runtime services to specify and determine the security
         state of the next image after BL3-1. This has been done by adding
         the `bl31_set_next_image_type()` & `bl31_get_next_image_type()`
         apis. The default security state is non-secure. The platform api
         `bl31_get_next_image_info()` has been modified to let the platform
         decide which is the next image in the desired security state.
      
      2. BL3-1 exports the `bl31_prepare_next_image_entry()` function to
         program entry into the target security state. It uses the apis
         introduced in 1. to do so.
      
      3. BL3-1 reads the information populated by BL2 about the BL3-2 image
         into its internal data structures.
      
      4. BL3-1 introduces a weakly defined reference `bl32_init()` to allow
         initialisation of a BL3-2 image. A runtime service like the Secure
         payload dispatcher will define this function if present.
      
      Change-Id: Icc46dcdb9e475ce6575dd3f9a5dc7a48a83d21d1
      35ca3511
    • Achin Gupta's avatar
      Add support for BL3-2 in BL2 · a3050ed5
      Achin Gupta authored
      
      
      This patch adds support for loading a BL3-2 image in BL2. In case a
      BL3-2 image is found, it also passes information to BL3-1 about where it
      is located and the extents of memory available to it. Information about
      memory extents is populated by platform specific code.
      
      The documentation has also been updated to reflect the above changes.
      
      Change-Id: I526b2efb80babebab1318f2b02e319a86d6758b0
      Co-authored-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      a3050ed5
    • Achin Gupta's avatar
      Rework BL2 to BL3-1 hand over interface · e4d084ea
      Achin Gupta authored
      This patch reworks BL2 to BL3-1 hand over interface by introducing a
      composite structure (bl31_args) that holds the superset of information
      that needs to be passed from BL2 to BL3-1.
      
        - The extents of secure memory available to BL3-1
        - The extents of memory available to BL3-2 (not yet implemented) and
          BL3-3
        - Information to execute BL3-2 (not yet implemented) and BL3-3 images
      
      This patch also introduces a new platform API (bl2_get_bl31_args_ptr)
      that needs to be implemented by the platform code to export reference to
      bl31_args structure which has been allocated in platform-defined memory.
      
      The platform will initialize the extents of memory available to BL3-3
      during early platform setup in bl31_args structure. This obviates the
      need for bl2_get_ns_mem_layout platform API.
      
      BL2 calls the bl2_get_bl31_args_ptr function to get a reference to
      bl31_args structure. It uses the 'bl33_meminfo' field of this structure
      to load the BL3-3 image. It sets the entry point information for the
      BL3-3 image in the 'bl33_image_info' field of this structure. The
      reference to this structure is passed to the BL3-1 image.
      
      Also fixes issue ARM-software/tf-issues#25
      
      Change-Id: Ic36426196dd5ebf89e60ff42643bed01b3500517
      e4d084ea
  2. 17 Feb, 2014 6 commits
    • Achin Gupta's avatar
      Increase coherent stack sizes · ca823d2c
      Achin Gupta authored
      This patch increases coherent stack size for both debug and release
      builds in order to accommodate stack-heavy printf() and extended EL3
      functionality
      
      Change-Id: I30ef30530a01517a97e63d703873374828c09f20
      ca823d2c
    • Jeenu Viswambharan's avatar
      Move translation tables into separate section · 74cbb839
      Jeenu Viswambharan authored
      This patch moves the translation tables into their own section. This
      saves space that would otherwise have been lost in padding due to page
      table alignment constraints. The BL31 and BL32 bases have been
      consequently adjusted.
      
      Change-Id: Ibd65ae8a5ce4c4ea9a71a794c95bbff40dc63e65
      74cbb839
    • Harry Liebel's avatar
      Add Firmware Image Package (FIP) driver · 561cd33e
      Harry Liebel authored
      The Firmware Image Package (FIP) driver allows for data to be loaded
      from a FIP on platform storage. The FVP supports loading bootloader
      images from a FIP located in NOR FLASH.
      
      The implemented FVP policy states that bootloader images will be
      loaded from a FIP in NOR FLASH if available and fall back to loading
      individual images from semi-hosting.
      
      NOTE:
      - BL3-3(e.g. UEFI) is loaded into DRAM and needs to be configured
        to run from the BL33_BASE address. This is currently set to
        DRAM_BASE+128MB for the FVP.
      
      Change-Id: I2e4821748e3376b5f9e467cf3ec09509e43579a0
      561cd33e
    • James Morrissey's avatar
      Implement load_image in terms of IO abstraction · 9d72b4ea
      James Morrissey authored
      The modified implementation uses the IO abstraction rather than
      making direct semi-hosting calls.  The semi-hosting driver is now
      registered for the FVP platform during initialisation of each boot
      stage where it is used.  Additionally, the FVP platform includes a
      straightforward implementation of 'plat_get_image_source' which
      provides a generic means for the 'load_image' function to determine
      how to access the image data.
      
      Change-Id: Ia34457b471dbee990c7b3c79de7aee4ceea51aa6
      9d72b4ea
    • James Morrissey's avatar
      Add IO abstraction framework · f2f9bb5e
      James Morrissey authored
      This is intended primarily for use as a storage abstraction.
      It allows operations such as image-loading to be implemented
      in a platform-independent fashion.  Each platform registers
      a set of IO drivers during initialisation.  The platform must
      also provide a function that will return a device and a specifier
      that can be used to access specified content.
      
      Clients of the API will primarily use device and entity handles.
      The term "entity" is deliberately vague, to allow for different
      representations of content accessed using different types of
      specifier, but will often be interpreted as a "file" where the
      specifier will normally be its path.
      
      This commit builds, but is intended to be paired with a sample
      implementation of "load_image" using a semi-hosting driver on FVP.
      
      Change-Id: Id3b52f1c0eb9ce76b44b99fc6b6460803668cc86
      f2f9bb5e
    • James Morrissey's avatar
      Fix asserts appearing in release builds · 40a6f647
      James Morrissey authored
      Also fix warnings generated in release builds when assert code
      is absent.
      
      Change-Id: I45b9173d3888f9e93e98eb5b4fdc06727ba5cbf4
      40a6f647
  3. 23 Jan, 2014 1 commit
    • Achin Gupta's avatar
      fvp: clear a pending cluster power off request · b2187ab9
      Achin Gupta authored
      The last CPU in a cluster is responsible for issuing the cluster power
      down request to the FVP power controller. If another CPU in this
      cluster wakes up before the last CPU enters WFI then the cluster power
      down request remains pending. If this request is not cancelled and the
      newly woken up CPU enters a simple WFI later, the power controller
      powers the cluster down. This leads to unpredictable behaviour.
      
      This patch fixes this issue by ensuring that the first CPU to wake up
      in a cluster writes its MPIDR to the power controller's PPONR. This
      cancels any pending cluster power down request.
      
      Change-Id: I7e787adfd6c9a0bd7308390e3309d46f35c01086
      b2187ab9
  4. 20 Jan, 2014 3 commits
  5. 17 Jan, 2014 4 commits
    • Jeenu Viswambharan's avatar
      Change comments in assembler files to help ctags · 3a4cae05
      Jeenu Viswambharan authored
      Ctags seem to have a problem with generating tags for assembler symbols
      when a comment immediately follows an assembly label.
      
      This patch inserts a single space character between the label
      definition and the following comments to help ctags.
      
      The patch is generated by the command:
      
        git ls-files -- \*.S | xargs sed -i 's/^\([^:]\+\):;/\1: ;/1'
      
      Change-Id: If7a3c9d0f51207ea033cc8b8e1b34acaa0926475
      3a4cae05
    • Harry Liebel's avatar
      Probe for GICv3 re-distributors on core bring-up · eaec590e
      Harry Liebel authored
      The GICv3 distributor can have more ports than CPUs are available in
      the system. Probe all re-distributors and use the matching affinity
      levels as specified by each core and re-distributor to decide which
      re-distributor to use with which CPU core.
      
      If a core cannot be matched with a re-distributor, the core panics and
      is placed in an endless loop.
      
      Change-Id: Ie393cfe07c7449a2383959e3c968664882e18afc
      eaec590e
    • Dan Handley's avatar
      Update year in copyright text to 2014 · e83b0cad
      Dan Handley authored
      Change-Id: Ic7fb61aabae1d515b9e6baf3dd003807ff42da60
      e83b0cad
    • Ian Spray's avatar
      Move GIC setup to a separate file · 8468739c
      Ian Spray authored
      GIC setup code which used to be in bl31_plat_setup.c is now in fvp_gic.c
      to simplify future changes to other bootloader stages.  This patch moves
      code from bl31_plat_setup.c to fvp_gic.c, simplifies the include file
      list for bl31_plat_setup.c, moves GIC declarations from the bl31.h header
      file into the platform.h, and reworks files according to coding style
      guide.
      
      Change-Id: I48d82a4ba33e7114dcc88f9ca98767a06cf8f417
      8468739c
  6. 12 Dec, 2013 2 commits
    • Sandrine Bailleux's avatar
      Make BL31's ns_entry_info a single-cpu area · 93ca221c
      Sandrine Bailleux authored
      ns_entry_info used to be a per-cpu array.  This is a waste of space
      because it is only accessed by the primary CPU on the cold boot path.
      This patch reduces ns_entry_info to a single-cpu area.
      
      Change-Id: I647c70c4e76069560f1aaad37a1d5910f56fba4c
      93ca221c
    • Sandrine Bailleux's avatar
      Remove useless copies of meminfo structures · ee12f6f7
      Sandrine Bailleux authored
      Platform setup code has to reserve some memory for storing the
      memory layout information.  It is populated in early platform setup
      code.
      
      blx_get_sec_mem_layout() functions used to return a copy of this
      structure.  This patch modifies blx_get_sec_mem_layout() functions
      so that they now directly return a pointer to their memory layout
      structure.  It ensures that the memory layout returned by
      blx_get_sec_mem_layout() is always up-to-date and also avoids a
      useless copy of the meminfo structure.
      
      Also rename blx_get_sec_mem_layout() to blx_plat_sec_mem_layout()
      to make it clear those functions are platform specific.
      
      Change-Id: Ic7a6f9d6b6236b14865ab48a9f5eff545ce56551
      ee12f6f7
  7. 05 Dec, 2013 6 commits
    • Achin Gupta's avatar
      remove check on non-secure entrypoint parameter · 2d94d4a0
      Achin Gupta authored
      In fvp_affinst_on/suspend, the non-secure entrypoint is always
      expected to lie in the DRAM. This check will not be valid if
      non-secure code executes directly out of flash e.g. a baremetal
      test. This patch removes this check.
      
      Change-Id: I0436e1138fc394aae8ff1ea59ebe38b46a440b61
      2d94d4a0
    • Achin Gupta's avatar
      psci: fix error due to a non zero context id · c8afc789
      Achin Gupta authored
      In the previous psci implementation, the psci_afflvl_power_on_finish()
      function would run into an error condition if the value of the context
      id parameter in the cpu_on and cpu_suspend psci calls was != 0. The
      parameter was being restored as the return value of the affinity level
      0 finisher function. A non zero context id would be treated as an
      error condition. This would prevent successful wake up of the cpu from
      a power down state. Also, the contents of the general purpose
      registers were not being cleared upon return to the non-secure world
      after a cpu power up. This could potentially allow the non-secure
      world to view secure data.
      
      This patch ensures that all general purpose registers are set to ~0
      prior to the final eret that drops the execution to the non-secure
      world. The context id is used to initialize the general purpose
      register x0 prior to re-entry into the non-secure world and is no
      longer restored as a function return value. A platform helper
      (platform_get_stack()) has been introduced to facilitate this change.
      
      Change-Id: I2454911ffd75705d6aa8609a5d250d9b26fa097c
      c8afc789
    • Achin Gupta's avatar
      clear wakeup enable bit upon resuming from suspend · b127cdb8
      Achin Gupta authored
      The FVP specific code that gets called after a cpu has been physically
      powered on after having been turned off or suspended earlier does not
      clear the PWRC.PWKUPR.WEN bit. Not doing so causes problems if: a cpu
      is suspended, woken from suspend, powered down through a cpu_off call
      & receives a spurious interrupt. Since the WEN bit is not cleared
      after the cpu woke up from suspend, the spurious wakeup will power the
      cpu on. Since the cpu_off call clears the jump address in the mailbox
      this spurious wakeup will cause the cpu to crash.
      
      This patch fixes this issue by clearing the WEN bit whenever a cpu is
      powered up.
      
      Change-Id: Ic91f5dffe1ed01d76bc7fc807acf0ecd3e38ce5b
      b127cdb8
    • Dan Handley's avatar
      Enable third party contributions · ab2d31ed
      Dan Handley authored
      - Add instructions for contributing to ARM Trusted Firmware.
      
      - Update copyright text in all files to acknowledge contributors.
      
      Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5
      ab2d31ed
    • Sandrine Bailleux's avatar
      Properly initialise the C runtime environment · 65f546a1
      Sandrine Bailleux authored
      This patch makes sure the C runtime environment is properly
      initialised before executing any C code.
      
        - Zero-initialise NOBITS sections (e.g. the bss section).
        - Relocate BL1 data from ROM to RAM.
      
      Change-Id: I0da81b417b2f0d1f7ef667cc5131b1e47e22571f
      65f546a1
    • Sandrine Bailleux's avatar
      Various improvements/cleanups on the linker scripts · 8d69a03f
      Sandrine Bailleux authored
        - Check at link-time that bootloader images will fit in memory
          at run time and that they won't overlap each other.
        - Remove text and rodata orphan sections.
        - Define new linker symbols to remove the need for platform setup
          code to know the order of sections.
        - Reduce the size of the raw binary images by cutting some sections
          out of the disk image and allocating them at load time, whenever
          possible.
        - Rework alignment constraints on sections.
        - Remove unused linker symbols.
        - Homogenize linker symbols names across all BLs.
        - Add some comments in the linker scripts.
      
      Change-Id: I47a328af0ccc7c8ab47fcc0dc6e7dd26160610b9
      8d69a03f
  8. 27 Nov, 2013 4 commits
    • Sandrine Bailleux's avatar
      fvp: Remove call to bl2_get_ns_mem_layout() function · 942f4053
      Sandrine Bailleux authored
      On FVP platforms, for now it is assumed that the normal-world
      bootloader is already sitting in its final memory location.
      Therefore, BL2 doesn't need to load it and so it doesn't need
      to know the extents of the non-trusted DRAM.
      
      Change-Id: I33177ab43ca242edc8958f2fa8d994e7cf3e0843
      942f4053
    • Sandrine Bailleux's avatar
      AArch64: Remove EL-agnostic TLB helper functions · 295538bc
      Sandrine Bailleux authored
      Also, don't invalidate the TLBs in disable_mmu() function, it's better
      to do it in enable_mmu() function just before actually enabling the
      MMU.
      
      Change-Id: Ib32d6660019b0b2c17254156aad4be67ab4970e1
      295538bc
    • Sandrine Bailleux's avatar
      fvp: Remove unnecessary initializers · 204aa03d
      Sandrine Bailleux authored
      Global and static variables are expected to be initialised to zero
      by default.  This is specified by the C99 standard. This patch
      removes some unnecessary initialisations of such variables.
      
      It fixes a compilation warning at the same time:
        plat/fvp/bl31_plat_setup.c:82:3: warning: missing braces around
        initializer [-Wmissing-braces]
           section("tzfw_coherent_mem"))) = {0};
           ^
        plat/fvp/bl31_plat_setup.c:82:3: warning: (near initialization for
        ‘ns_entry_info[0]’) [-Wmissing-braces]
      
      Note that GCC should not have emitted this warning message in the
      first place.  The C Standard permits braces to be elided around
      subaggregate initializers.  See this GCC bug report:
      http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119
      
      Change-Id: I13cb0c344feb9803bca8819f976377741fa6bc35
      204aa03d
    • Sandrine Bailleux's avatar
      Move generic architectural setup out of blx_plat_arch_setup(). · c10bd2ce
      Sandrine Bailleux authored
      blx_plat_arch_setup() should only perform platform-specific
      architectural setup, e.g. enabling the MMU.  This patch moves
      generic architectural setup code out of blx_plat_arch_setup().
      
      Change-Id: I4ccf56b8c4a2fa84909817779a2d97a14aaafab6
      c10bd2ce
  9. 14 Nov, 2013 2 commits
  10. 25 Oct, 2013 1 commit