1. 29 Oct, 2014 1 commit
    • Soby Mathew's avatar
      Add support for level specific cache maintenance operations · 8e857916
      Soby Mathew authored
      This patch adds level specific cache maintenance functions
      to cache_helpers.S. The new functions 'dcsw_op_levelx',
      where '1 <= x <= 3', allow to perform cache maintenance by
      set/way for that particular level of cache.  With this patch,
      functions to support cache maintenance upto level 3 have
      been implemented since it is the highest cache level for
      most ARM SoCs.
      
      These functions are now utilized in CPU specific power down
      sequences to implement them as mandated by processor specific
      technical reference manual.
      
      Change-Id: Icd90ce6b51cff5a12863bcda01b93601417fd45c
      8e857916
  2. 28 Oct, 2014 3 commits
  3. 22 Oct, 2014 1 commit
    • Juan Castillo's avatar
      FVP: keep shared data in Trusted SRAM · 20d51cad
      Juan Castillo authored
      This patch deprecates the build option to relocate the shared data
      into Trusted DRAM in FVP. After this change, shared data is always
      located at the base of Trusted SRAM. This reduces the complexity
      of the memory map and the number of combinations in the build
      options.
      
      Fixes ARM-software/tf-issues#257
      
      Change-Id: I68426472567b9d8c6d22d8884cb816f6b61bcbd3
      20d51cad
  4. 21 Oct, 2014 1 commit
    • Vikram Kanigiri's avatar
      Juno: Support entry into a standby state · fc680456
      Vikram Kanigiri authored
      This patch adds support on the Juno platform for entering a wfi in
      response to a PSCI CPU_SUSPEND call where the state type is a
      standby state.
      
      Change-Id: I0a102dee1f8d2ad936c63ad1d1d3ad001a4a4768
      fc680456
  5. 14 Oct, 2014 1 commit
    • Juan Castillo's avatar
      Juno: Reserve some DDR-DRAM for secure use · 740134e6
      Juan Castillo authored
      This patch configures the TrustZone Controller in Juno to split
      the 2GB DDR-DRAM memory at 0x80000000 into Secure and Non-Secure
      regions:
      
      - Secure DDR-DRAM: top 16 MB, except for the last 2 MB which are
        used by the SCP for DDR retraining
      - Non-Secure DDR-DRAM: remaining DRAM starting at base address
      
      Build option PLAT_TSP_LOCATION selects the location of the secure
      payload (BL3-2):
      
      - 'tsram' : Trusted SRAM (default option)
      - 'dram'  : Secure region in the DDR-DRAM (set by the TrustZone
                  controller)
      
      The MMU memory map has been updated to give BL2 permission to load
      BL3-2 into the DDR-DRAM secure region.
      
      Fixes ARM-software/tf-issues#233
      
      Change-Id: I6843fc32ef90aadd3ea6ac4c7f314f8ecbd5d07b
      740134e6
  6. 10 Oct, 2014 1 commit
  7. 09 Oct, 2014 1 commit
    • Juan Castillo's avatar
      Juno: Use TZC-400 driver calls · ef538c6f
      Juan Castillo authored
      This patch replaces direct accesses to the TZC-400 registers by the
      appropiate calls to the generic driver available in the Trusted
      Firmware in order to initialize the TrustZone Controller.
      
      Functions related to the initialization of the secure memory,
      like the TZC-400 configuration, have been moved to a new file
      'plat_security.c'. This reorganization makes easier to set up
      the secure memory from any BL stage.
      
      TZC-400 initialization has been moved from BL1 to BL2 because BL1
      does not access the non-secure memory. It is BL2's responsibility
      to enable and configure the TZC-400 before loading the next BL
      images.
      
      In Juno, BL3-0 initializes some of the platform peripherals, like
      the DDR controller. Thus, BL3-0 must be loaded before configuring
      the TrustZone Controller. As a consequence, the IO layer
      initialization has been moved to early platform initialization.
      
      Fixes ARM-software/tf-issues#234
      
      Change-Id: I83dde778f937ac8d2996f7377e871a2e77d9490e
      ef538c6f
  8. 25 Sep, 2014 2 commits
  9. 23 Sep, 2014 1 commit
  10. 22 Sep, 2014 1 commit
    • Soby Mathew's avatar
      Remove BSS section access by 'plat_print_gic' during crash reporting · 6ab03912
      Soby Mathew authored
      This patch avoids the problem of crash reporting mechanism accessing
      global data in BSS by 'plat_print_gic_regs' for FVP platforms. Earlier
      it depended on the global 'plat_config' object for the GIC Base address
      in FVP platforms which would have caused exception if it were accessed
      before the BSS was initialized. It is now fixed by dynamically
      querying the V2M_SYS_ID to find the FVP model type and accordingly
      selecting the appropriate GIC Base address.
      
      This patch also fixes the 'plat_print_gic_regs' to use the correct GIC
      Distributor base address for printing GICD_IS_PENDR register values
      for both Juno and FVP platforms.
      
      Fixes ARM-Software/tf-issues#236
      
      Change-Id: I545c7b908b3111419bf27db0575ce86acf86784b
      6ab03912
  11. 19 Sep, 2014 2 commits
  12. 17 Sep, 2014 1 commit
  13. 16 Sep, 2014 4 commits
    • Jens Wiklander's avatar
      Add opteed based on tspd · aa5da461
      Jens Wiklander authored
      Adds a dispatcher for OP-TEE based on the test secure payload
      dispatcher.
      
      Fixes arm-software/tf-issues#239
      aa5da461
    • Jens Wiklander's avatar
      Initialize SCTLR_EL1 based on MODE_RW bit · ae213cee
      Jens Wiklander authored
      Initializes SCTLR_EL1 based on MODE_RW bit in SPSR for the entry
      point. The RES1 bits for SCTLR_EL1 differs for Aarch64 and Aarch32
      mode.
      ae213cee
    • achingupta's avatar
      Merge pull request #210 from soby-mathew/sm/makefile_bl_stages · 087b67a6
      achingupta authored
      Add support for specifying pre-built BL binaries in Makefile
      087b67a6
    • Soby Mathew's avatar
      Add support for specifying pre-built BL binaries in Makefile · 27713fb4
      Soby Mathew authored
      This patch adds support for supplying pre-built BL binaries for BL2,
      BL3-1 and BL3-2 during trusted firmware build. Specifying BLx = <path_to_BLx>
      in the build command line, where 'x' is any one of BL2, BL3-1 or BL3-2, will
      skip building that BL stage from source and include the specified binary in
      final fip image.
      
      This patch also makes BL3-3 binary for FIP optional depending on the
      value of 'NEED_BL33' flag which is defined by the platform.
      
      Fixes ARM-software/tf-issues#244
      Fixes ARM-software/tf-issues#245
      
      Change-Id: I3ebe1d4901f8b857e8bb51372290978a3323bfe7
      27713fb4
  14. 02 Sep, 2014 1 commit
    • Soby Mathew's avatar
      Reset CNTVOFF_EL2 register before exit into EL1 on warm boot · 14c0526b
      Soby Mathew authored
      This patch resets the value of CNTVOFF_EL2 before exit to EL1 on
      warm boot. This needs to be done if only the Trusted Firmware exits
      to EL1 instead of EL2, otherwise the hypervisor would be responsible
      for this.
      
      Fixes ARM-software/tf-issues#240
      
      Change-Id: I79d54831356cf3215bcf1f251c373bd8f89db0e0
      14c0526b
  15. 28 Aug, 2014 4 commits
  16. 27 Aug, 2014 8 commits
  17. 21 Aug, 2014 7 commits