GitLab

* changes:
  mediatek: mt8192: add rtc power off sequence
  mediatek: mt8192: Fix non-MISRA compliant code
  mediatek: mt8192: Fix non-MISRA compliant code
  mediatek: mt8192: Add MPU support

* changes:
  allwinner: Add SPC security setup for H6
  allwinner: Add R_PRCM security setup for H6

* changes:
  allwinner: Use RSB for the PMIC connection on H6
  allwinner: Return the PMIC to I2C mode after use
  allwinner: Always use a 3MHz RSB bus clock

* changes:
  fdts: tc0: Add reserved-memory node for OP-TEE
  plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
  docs: arm: Add OPTEE_SP_FW_CONFIG
  plat: tc0: enable opteed support
  plat: arm: Increase SP max size

Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core.  The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics.  This issue is
present in revisions r0p0 - r4p1  but this workaround only applies to
revisions r3p0 - r4p1, there is no workaround for older versions.

SDEN can be found here:
https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327

add mt6359p rtc power off sequence and enable k_eosc mode
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.com>
Change-Id: I65450c63c44ccb5082541dbbe28b8aa0a95ecc56

CID 364146: Control flow issues (DEADCODE)

Since the value of PSTATE_PWR_LVL_MASK and the value the of PLAT_MAX_PWR_LVL
are equal on mt8192, the following equation never hold.

if (aff_lvl > PLAT_MAX_PWR_LVL) {
	return PSCI_E_INVALID_PARAMS;
}

Remove the deadcode to comply with MISRA standard.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I71d0aa826eded8c3b5af961e733167ae40699398

CID 364144: Integer handling issues (NO_EFFECT)

The unsigned value is always greater-than-or-equal-to-zero.
Remove such check.

Change-Id: Ia395eb32f55a7098d2581ce7f548b7e1112beaa0
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>

1 Add Domain1(PCIe device) protect address: 0x80000000~0x83FF0000.
2 Add Domain2(SSPM/SPM/DPM/MCUPM) protect address: 0x40000000~0x1FFFF0000.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I4aaed37150076ae5943484c4adadac999a3d1762

RD-N2 platform has been updated to use six GIC ITS blocks. This results
in change in base address of the GIC Redistributor to accomodate two
new GIC ITS blocks. Update the base address of GICR to reflect the same.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I740a547328fb9a9f25d7a09c08e61bdbc8bf781c

Add reserved-memory region for OP-TEE and mark as no-map. This memory
region is used by OP-TEE as non-secure shared RAM.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I5a22999a8c5550024d0f47e848d35924017df245

This patch adds support to enable OP-TEE as S-EL1 SP with SPMC at S-EL2
     - create SPMC manifest file with OP-TEE as SP
     - add support for ARM_SPMC_MANIFEST_DTS build option
     - add optee entry with ffa as method in tc0.dts
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ia9b5c22c6f605d3886914bbac8ac45e8365671cb

This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ie45f075cf04182701007f87aa0c8912cd567157a

Enable SPD=opteed support for tc0 platform.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ieb038d645c68fbe6b5a211c7279569e21b476fc3

Increase SP max size for latest OP-TEE build with debug and
stats enabled.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I4593884e0deb39ada10009f6876d815136f8ee65

RSB is faster and more efficient, and it has a simpler driver. As long
as the PMIC is returned to I2C mode after use, the rich OS can later use
either bus.

Change-Id: I0c5f32e88a090c8c5cccb81bd24596b301ab9da7
Signed-off-by: Samuel Holland <samuel@sholland.org>

This gives the rich OS the flexibility to choose between I2C and RSB
communication. Since a runtime address can only be assigned once after
entering RSB mode, it also lets the rich OS choose any runtime address.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id49c124c5e925985fc31c0ba38c7fb6c941aafa8

None of the other drivers (Linux, U-Boot, Crust) need to lower the bus
clock frequency to switch the PMIC to RSB mode. That logic is not needed
here, either. The hardware takes care of running this transaction at the
correct bus frequency.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idcfe933df4da75d5fd5a4f3e362da40ac26bdad1

BL31 reports the following warning during boot:

  WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing!

Resolve this by enabling the workaround on the affected platforms.

Change-Id: Ia1d5075370be5ae67b7bece96ec0069d9692b14c
Signed-off-by: Samuel Holland <samuel@sholland.org>

While the Allwinner platform code nominally supported a custom
PRELOADED_BL33_BASE, some references to the BL33 load address used
another constant: PLAT_SUNXI_NS_IMAGE_OFFSET. To allow the DTB search
code to work if a U-Boot BL33 is loaded to a custom address,
consistently use PRELOADED_BL33_BASE. And to avoid this confusion in
the future, remove the other constant.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie6b97ae1fdec95d784676aef39200bef161471b0

The H6 has a "secure port controller" similar to the A64/H5, but with
more ports and a different register layout. Split the platform-specific
parts out into a header, and add the missing MMIO base address.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I3703868bc595459ecf9568b9d1605cb1be014bf5

H6 has a reorganized R_PRCM compared to A64/H5, with the security switch
at a different offset. Until now, we did not notice, because the switch
has no effect unless the secure mode e-fuse is blown.

Since we are adding more platform-specific CCU registers, move them to
their own header, and out of the memory map (where they do not belong).
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie77476db0515080954eaa2e32bf6c3de657cda86

* changes:
  doc: Update list of supported FVP platforms
  board/rdn2: add board support for rdn2 platform
  plat/arm/sgi: adapt to changes in memory map
  plat/arm/sgi: add platform id value for rdn2 platform
  plat/arm/sgi: platform definitions for upcoming platforms
  plat/arm/sgi: refactor header file inclusions
  plat/arm/sgi: refactor the inclusion of memory mapping

If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.

If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.

This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e

This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults to
'none'. This option translates into compiler option
'-march=armvX[.Y]-a+[no]feature+...'.

Change-Id: I37742f270a898f5d6968e146cbcc04cbf53ef2ad
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Icef550072296d6aba89a0827dd72d0b86047556f

* changes:
  plat: xilinx: versal: Add support of register notifier
  plat: xilinx: versal: Add support to get clock rate value
  plat: xilinx: versal: Add support of set max latency for the device
  plat: versal: Add InitFinalize API call
  xilinx: versal: Updated Response of QueryData API call
  plat:xilinx:versal: Use defaults when PDI is without sw partitions
  plat: xilinx: Mask unnecessary bytes of return error code
  xilinx: versal: Skip store/restore of GIC during CPU idle
  plat: versal: Update API list in feature check
  xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()

* changes:
  spm: provide number of vCPUs and VM size for first SP
  spm: remove chosen node from SPMC manifests
  spm: move OP-TEE SP manifest DTS to FVP platform
  spm: update OP-TEE SP manifest with device-regions node
  spm: remove device-memory node from SPMC manifests

Updated the documentation for the FIP generation process using
SP images.

Change-Id: I4df7f379f08f33adba6f5c82904291576972e106
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Updated the list of supported FVP platforms with support for RD-N2 FVP.

Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

Add the initial board support for RD-N2 platform.

Change-Id: I8325885bf248dd92191d6fc92a2da91c23118f8c
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

Upcoming RD platforms will have an updated memory map for the various
pheripherals on the system. So, for the newer platforms, handle the
memory mapping and other platform specific functionality separately
from the existing platforms.

Change-Id: Iab1355a4c8ea1f6db4f79fcdd6eed907903b6a18
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>