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Add support to identify HopeRun HiHope RZ/G2N board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib47aba84b63488247f6e9da1f5878140129766ce

Select MMC_CH1 for eMMC on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib584b5203f38423ffe2ab52c6e6922f5b34a33ee

Add QoS support for RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I663b50d9fb41b9b20a6b54795278659b2b184bc4

Add pin control support for RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib5eb4f3b1b75e158ec13c4eefdbe9688344206a3

Add support for initializing DRAM on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0

Add support to identify HopeRun HiHope RZ/G2H board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I6b28350ef50595fea9a1b1b7353fcabaeb935970

Select MMC_CH1 for eMMC on RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I1bdfa462fd98b144042c014701b342b87e1efc9d

Add QoS support for RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: If7d8940148fc31887568fd501c6cab609e715ba4

Add pin control support for RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I06dc259d7d26a5a5313e8731ea72f846bfca09ed

Add support for initializing DRAM on RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9

Switch using common ddr driver code from renesas/common/ddr directory
for RZ/G2M SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I807dcb0bc5186bd32bc1c577945d28634bb10e1f

Move ddr driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I9aef73d3e9a027a127ce7483b72d339559866727

* changes:
  plat/marvell: remove subversion from Marvell make files
  drivers/marvell: check if TRNG unit is present
  plat/marvell: a8k: move efuse definitions to separate header
  plat/marvell/armada: fix TRNG return SMC handling
  drivers: marvell: comphy: add rx training on 10G port
  plat/marvell/armada: postpone MSS CPU startup to BL31 stage
  plat: marvell: armada: a8k: Fix LD selector mask
  plat/marvell/armada: allow builds without MSS support
  drivers: marvell: misc-dfx: extend dfx whitelist
  drivers: marvell: add support for secure read/write of dfx register-set
  ddr_phy: use smc calls to access ddr phy registers
  drivers: marvell: thermal: use dedicated function for thermal SiPs
  drivers: marvell: add thermal sensor driver and expose it via SIP service
  fix: plat: marvell: fix MSS loader for A8K family

Subversion is not reflecting the Marvell sources variant anymore.
This patch removes version.mk from Marvell plafroms.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I8f3afbe3fab3a38da68876f77455f449f5fe0179

Some Marvell SoCs may have crypto engine disabled in the HW.
This patch checks the AP LD0 efuse for crypto engine/TRNG
presence before initializing the driver.

Change-Id: I441e7c69a137106bd36302b028b04c0b31896dbd
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47314

Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>

Move efuse definitions to a separate header file for later
usage with other FW modules.

Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47313

Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>

Use single 64b register for the return value instead of two 32b.
Report an error if caller requested larger than than 64b random
number in a single SMC call.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Ib8756cd3c0808b78c359f90c6f6913f7d16ac360
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/33280

Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.
Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763

Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2.
However, (especailly in secure boot mode), some bus attributes should be
changed from defaults before the MSS CPU tries to access shared resources.
This patch starts to use CP MSS SRAM for FW load in both secure and
non-secure boot modes.
The FW loader inserts a magic number into MSS SRAM as an indicator of
successfully loaded FS during the BL2 stage and skips releasing the MSS
CPU from the reset state.
Then, at BL31 stage, the MSS CPU is released from reset following the
call to cp110_init function that handles all the required bus attributes
configurations.

Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890

Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>

Fixed a bug that the actually bit number was used as a mask to
select LD0 or LD1 fuse
Signed-off-by: Guo Yi <yguo@cavium.com>
Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146

Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and will not support PM, FC and other features implemented
in these FW images.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769

Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

Linux cpu clk driver requires access to some dfx registers. By adding
these registers to the white list, we enable access to them from
non-secure world.

Change-Id: Ic05c96b375121c025bfb41c2ac9474a530720155
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25187

Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.

This will allow non-secure word drivers access some white-listed
registers related to e.g.:  Sample at reset, efuses, SoC type and
revision ID accesses.

Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055

Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Added smc calls support to access ddr phy registers.

Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870
Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20791

Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Since more drivers which uses dfx register set need to be handled with
use of SiP services, use dedicated and more meaningful name for thermal
SiP services.

Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25054

Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), accessing thermal
registers which are part of dfx register set, will not be possible from
lower exception levels. Due to above expose thermal driver as a SiP
service.  This will allow Linux and U-Boot thermal driver to initialise
and perform various operations on thermal sensor.

The thermal sensor driver is based on Linux
drivers/thermal/armada_thermal.c.

Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/20581

Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>

Wrong brakets caused MSS FW load timeout error:
ERROR:   MSS DMA failed (timeout)
ERROR:   MSS FW chunk 0 load failed
ERROR:   SCP Image load failed

This patch fixes the operator precedence in MSS FW load.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I78c215606bde112f40429926c51f5fa1e4334c13

The current SPM_MM implementations expects the SP image addresses
as static macros. This means platforms wanting to use dynamically
allocated memory addresses are left out. This patch gets sp_boot_info
at the beginning of spm_sp_setup function and uses member variables
of sp_boot_info to setup the context. So member variables of
struct sp_boot_info and consequently the context can be initialized
by static macros or dynamiclly allocated memory address..

Change-Id: I1cb75190ab8026b845ae20a9c6cc416945b5d7b9
Signed-off-by: Mayur Gudmeti <mgudmeti@nvidia.com>

* changes:
  drivers/arm/css/scmi: Update power domain protocol version to 2.0
  tc0: update GICR base address

UART register definition is the same on MediaTek platforms.
Move uart.h to common folder and remove the duplicate file.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Iea0931dfd606ae4a7ab475b9cb3a08dc6de68b36

The SCMI power domain protocol in firmware has been updated to v2.0,
thus update the corresponding version in TF-A too.
Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com>
Change-Id: If3920ff71136dce94b2780e29a47f24aa09876c0

The number of ITS have changed from 4 to 1, resulting
in GICR base address change.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7

Updated the documentation with latest Mbed TLS supported
version i.e. Mbed TLS v2.26.0

Fixes available in this version of Mbed TLS mainly affect
key generation/writing and certificates writing, which
are features used in the cert_create tool.

Release notes of Mbed TLSv2.26.0 are available here:
https://github.com/ARMmbed/mbedtls/releases/tag/v2.26.0



Change-Id: Ie15ee45d878b7681e15ec4bf64d54b416a31aa2f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

* changes:
  plat:xilinx:versal: Add JTAG DCC support
  plat:xilinx:zynqmp: Add JTAG DCC support
  drivers: dcc: Support JTAG DCC console