Skip to content

GitLab

Switch branch/tag
  1. 25 Feb, 2020 1 commit
  3. 24 Feb, 2020 1 commit
    • Petre-Ionut Tudor's avatar
      Read-only xlat tables for BL31 memory · 60e8f3cf
      Petre-Ionut Tudor authored 
      

This patch introduces a build flag which allows the xlat tables
to be mapped in a read-only region within BL31 memory. It makes it
much harder for someone who has acquired the ability to write to
arbitrary secure memory addresses to gain control of the
translation tables.

The memory attributes of the descriptors describing the tables
themselves are changed to read-only secure data. This change
happens at the end of BL31 runtime setup. Until this point, the
tables have read-write permissions. This gives a window of
opportunity for changes to be made to the tables with the MMU on
(e.g. reclaiming init code). No changes can be made to the tables
with the MMU turned on from this point onwards. This change is also
enabled for sp_min and tspd.

To make all this possible, the base table was moved to .rodata. The
penalty we pay is that now .rodata must be aligned to the size of
the base table (512B alignment). Still, this is better than putting
the base table with the higher level tables in the xlat_table
section, as that would cost us a full 4KB page.

Changing the tables from read-write to read-only cannot be done with
the MMU on, as the break-before-make sequence would invalidate the
descriptor which resolves the level 3 page table where that very
descriptor is located. This would make the translation required for
writing the changes impossible, generating an MMU fault.

The caches are also flushed.
Signed-off-by: default avatarPetre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: Ibe5de307e6dc94c67d6186139ac3973516430466
      60e8f3cf
  5. 20 Feb, 2020 14 commits
    • Varun Wadekar's avatar
      Tegra: spe: uninit console on a timeout · 8a47fe43
      Varun Wadekar authored 
      

There are chances a denial-of-service attack, if an attacker
removes the SPE firmware from the system. The console driver
would end up waiting for the firmware to respond indefinitely.
The console driver must detect such scenarios and uninit the
interface as a result.

This patch adds a timeout to the interaction with the SPE
firmware and uninits the interface if it times out.

Change-Id: I06f27a858baed25711d41105b4110865f1a01727
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8a47fe43
    • Varun Wadekar's avatar
      Tegra: handler to check support for System Suspend · 5d52aea8
      Varun Wadekar authored 
      

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".

This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".

Original change by: kalyani chidambaram <kalyanic@nvidia.com>

Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5d52aea8
    • Varun Wadekar's avatar
      Tegra: bpmp_ipc: improve cyclomatic complexity · 21368290
      Varun Wadekar authored 
      

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

    complexity < 10 is accepted
    10 <= complexity < 20 has to be justified
    complexity >= 20 cannot be accepted

Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.

This patch removes redundant conditionals from 'ipc_send_req_atomic'
handler to reduce the McCabe Cyclomatic Complexity for this function

Change-Id: I20fef79a771301e1c824aea72a45ff83f97591d5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      21368290
    • Varun Wadekar's avatar
      Tegra: platform handler to relocate BL32 image · 6f47acdb
      Varun Wadekar authored 
      

This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZDRAM memory as the previous bootloader
relies on BL31 to do so.

Change-Id: Ibb864901e43aca5bf55d8c79e918b598c12e8a28
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      6f47acdb
    • Varun Wadekar's avatar
      Tegra: common: improve cyclomatic complexity · ee21281a
      Varun Wadekar authored 
      

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

    complexity < 10 is accepted
    10 <= complexity < 20 has to be justified
    complexity >= 20 cannot be accepted

Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.

This patch removes redundant conditionals from 'bl31_early_platform_setup'
handler to reduce the McCabe Cyclomatic Complexity for this function.

Change-Id: Ifb628e33269b388f9323639cd97db761a7e049c4
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ee21281a
    • kalyani chidambaram's avatar
      Tegra210: secure PMC hardware block · 37f76024
      kalyani chidambaram authored 
      

This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and System Resume.

The sc7entry-fw, running on the COP, needs access to the PMC block
to enter System Suspend state, so "unlock" the PMC block before
passing control to the COP.

Change-Id: I00e39a49ae6b9f8c8eafe0cf7ff63fe6a67fdccf
Signed-off-by: default avatarkalyani chidambaram <kalyanic@nvidia.com>
      37f76024
    • Varun Wadekar's avatar
      Tegra: delay_timer: support for physical secure timer · dd4f0885
      Varun Wadekar authored 
      

This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.

The secure timer is not accessible to the NS world and so eliminates
an important attack vector, where the Tegra timer source gets switched
off from the NS world leading to a DoS attack for the trusted world.

This timer is shared with the S-EL1 layer for now, but later patches
will mark it as exclusive to the EL3 exception mode.

Change-Id: I2c00f8cb4c48b25578971c626c314603906ad7cc
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      dd4f0885
    • Varun Wadekar's avatar
      include: move MHZ_TICKS_PER_SEC to utils_def.h · d4b29105
      Varun Wadekar authored 
      

This patch moves the MHZ_TICKS_PER_SEC macro to utils_def.h
for other platforms to use.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Change-Id: I6c4dc733f548d73cfdb3515ec9ad89a9efaf4407
      d4b29105
    • Pritesh Raithatha's avatar
      Tegra194: memctrl: lock mc stream id security config · 56e7d6a7
      Pritesh Raithatha authored 
      

This patch locks most of the stream id security config registers as
per HW guidance.

This patch keeps the stream id configs unlocked for the following
clients, to allow some platforms to still function, until they make
the transition to the latest guidance.

- ISPRA
- ISPFALR
- ISPFALW
- ISPWA
- ISPWA1
- ISPWB
- XUSB_DEVR
- XUSB_DEVW
- XUSB_HOSTR
- XUSB_HOSTW
- VIW
- VIFALR
- VIFALW

Change-Id: I66192b228a0a237035938f498babc0325764d5df
Signed-off-by: default avatarPritesh Raithatha <praithatha@nvidia.com>
      56e7d6a7
    • kalyani chidambaram's avatar
      Tegra210: resume PMC hardware block for all platforms · 3414bad8
      kalyani chidambaram authored 
      

The PMC hardware block resume handler was called for Tegra210
platforms, only if the sc7entry-fw was present on the device.
This would cause problems for devices that do not support this
firmware.

This patch fixes this logic and resumes the PMC block even if
the sc7entry-fw is not present on the device.

Change-Id: I6f0eb7878126f624ea98392f583ed45a231d27db
Signed-off-by: default avatarKalyani Chidambaram <kalyanic@nvidia.com>
      3414bad8
    • Varun Wadekar's avatar
      Tegra: macro for legacy WDT FIQ handling · b20a8b92
      Varun Wadekar authored 
      

This patch adds the macro to enable legacy FIQ handling to the common
Tegra makefile. The default value of this macro is '0'. Platforms that
need this support should enable it from their makefiles.

This patch also helps fix violation of Rule 20.9.

Rule 20.9 "All identifiers used in the controlling expression of #if
           of #elif preprocessing directives shall be #define'd before
           evaluation"

Change-Id: I4f0c9917c044b5b1967fb5e79542cd3bf6e91f18
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      b20a8b92
    • Varun Wadekar's avatar
      Tegra186: enable higher performance non-cacheable load forwarding · 103ea3f4
      Varun Wadekar authored 
      

This patch enables higher performance non-cacheable load forwarding for
Tegra186 platforms.

Change-Id: Ifceb304bfbd805f415bb6205c9679602ecb47b53
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      103ea3f4
    • Varun Wadekar's avatar
      Tegra210: enable higher performance non-cacheable load forwarding · 8baa16f8
      Varun Wadekar authored 
      

This patch enables higher performance non-cacheable load forwarding for
Tegra210 platforms.

Change-Id: I11d0ffc09aca97d37386f283f2fbd2483d51fd28
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8baa16f8
    • Abdul Halim, Muhammad Hadi Asyrafi's avatar
      intel: Fix Coverity Scan Defects · a62b47b8
      Abdul Halim, Muhammad Hadi Asyrafi authored 
      

Fix mailbox driver incompatible cast bug and control flow issue that
was flagged by Coverity Scan.
Signed-off-by: default avatarAbdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f34e98d24e40139d31cf7d5b9b973cd2d981065
      a62b47b8
  7. 18 Feb, 2020 4 commits
  9. 17 Feb, 2020 4 commits
    • Vishnu Banavath's avatar
      corstone700: set UART clocks to 32MHz · 6aa138de
      Vishnu Banavath authored 
      

Adding support for 32MHz UART clock and selecting it as the
default UART clock

Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c
Signed-off-by: default avatarVishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: default avatarAbdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
      6aa138de
    • Avinash Mehta's avatar
      corstone700: clean-up as per coding style guide · 93cf1f64
      Avinash Mehta authored 
      

Running checkpatch.pl on the codebase and making required changes

Change-Id: I7d3f8764cef632ab2a6d3c355c68f590440b85b8
Signed-off-by: default avatarAvinash Mehta <avinash.mehta@arm.com>
Signed-off-by: default avatarAbdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
      93cf1f64
    • Khandelwal's avatar
      Corstone700: add support for mhuv2 in arm TF-A · c6fe43b7
      Khandelwal authored 
      

Note: This patch implements in-band messaging protocol only.
ARM has launched a next version of MHU i.e. MHUv2 with its latest
subsystems. The main change is that the MHUv2 is now a distributed IP
with different peripheral views (registers) for the sender and receiver.

Another main difference is that MHUv1 duplex channels are now split into
simplex/half duplex in MHUv2. MHUv2 has a configurable number of
communication channels. There is a capability register (MSG_NO_CAP) to
find out how many channels are available in a system.

The register offsets have also changed for STAT, SET & CLEAR registers
from 0x0, 0x8 & 0x10 in MHUv1 to 0x0, 0xC & 0x8 in MHUv2 respectively.

0x0    0x4  0x8  0xC             0x1F
------------------------....-----
| STAT |    |    | SET |    |   |
------------------------....-----
      Transmit Channel

0x0    0x4  0x8   0xC            0x1F
------------------------....-----
| STAT |    | CLR |    |    |   |
------------------------....-----
        Receive Channel

The MHU controller can request the receiver to wake-up and once the
request is removed, the receiver may go back to sleep, but the MHU
itself does not actively put a receiver to sleep.

So, in order to wake-up the receiver when the sender wants to send data,
the sender has to set ACCESS_REQUEST register first in order to wake-up
receiver, state of which can be detected using ACCESS_READY register.
ACCESS_REQUEST has an offset of 0xF88 & ACCESS_READY has an offset
of 0xF8C and are accessible only on any sender channel.

This patch adds necessary changes in a new file required to support the
latest MHUv2 controller. This patch also needs an update in DT binding
for ARM MHUv2 as we need a second register base (tx base) which would
be used as the send channel base.

Change-Id: I1455e08b3d88671a191c558790c503eabe07a8e6
Signed-off-by: default avatarTushar Khandelwal <tushar.khandelwal@arm.com>
      c6fe43b7
    • XiaoDong Huang's avatar
      rockchip: fix definition of struct param_ddr_usage · 11a0a46a
      XiaoDong Huang authored 
      

In extreme cases, the number of secure regions is one more than
non-secure regions. So array "s_base" and "s_top"s size
in struct param_ddr_usage need to be adjust to "DDR_REGION_NR_MAX + 1".
Signed-off-by: default avatarXiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifc09da2c8f8afa1aebcc78f8fbc21ac95abdece2
      11a0a46a
  11. 15 Feb, 2020 4 commits
  13. 14 Feb, 2020 1 commit
    • Xi Chen's avatar
      mediatek: mt8183: protect 4GB~8GB dram memory · 95d3c46a
      Xi Chen authored 
      

The offset there is the virtual address space on the bus side (1-9GB for 8GB RAM),
and that emi_mpu_set_region_protection will translate to the physical memory space (0-8GB).

8GB is 33-bit (the memory bus width is 33-bit on this platform),
so 0x23FFFFFFFUL-EMI_PHY_OFFSET = 0x1_FFFF_FFFF.

Change-Id: I7be4759ed7546f7e15a5868b6f08988928c34075
Signed-off-by: default avatarXi Chen <xixi.chen@mediatek.com>
      95d3c46a
  15. 13 Feb, 2020 2 commits
  17. 12 Feb, 2020 9 commits