- 16 Jan, 2020 4 commits
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Hadi Asyrafi authored
Refactored system manager driver to be shared across both intel platform Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d
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Hadi Asyrafi authored
Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: -
Hadi Asyrafi authored
Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: -
Hadi Asyrafi authored
Combine both peripheral and bridge non-secure access code into a single callable function Signed-off-by:
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- 09 Jan, 2020 1 commit
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Madhukar Pappireddy authored
In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by:Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 28 Nov, 2019 3 commits
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Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: -
Hadi Asyrafi authored
Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: -
Hadi Asyrafi authored
Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by:
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- 19 Aug, 2019 1 commit
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Hadi Asyrafi authored
To provide glitchless clock to downstream logic even if clock toggles Signed-off-by:
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- 15 Aug, 2019 1 commit
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Hadi Asyrafi authored
Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by:
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- 14 Aug, 2019 1 commit
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by:
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- 07 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from aarch64 and include Signed-off-by:
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- 24 Jul, 2019 1 commit
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Ambroise Vincent authored
"result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]" This is treated as an error since commit 93c690eb ("Enable -Wshift-overflow=2 to check for undefined shift behavior") Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b Signed-off-by:
Ambroise Vincent <ambroise.vincent@arm.com>
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- 17 Jul, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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