- 10 Jul, 2020 5 commits
-
-
Sandrine Bailleux authored
-
Manish V Badarkhe authored
Included cot_descriptors.dtsi in platform device tree (fvp_tb_fw_config.dts). Also, updated the maximum size of tb_fw_config to 0x1800 in order to accomodate the device tree for CoT descriptors. Follow up patch will parse the device tree for these CoT descriptors and fill the CoT descriptor structures at runtime instead of using static CoT descriptor structures in the code base. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I90122bc713f6842b82fb019b04caf42629b4f45a
-
Sandrine Bailleux authored
-
Manish V Badarkhe authored
Added CoT descriptor nodes and properties in device tree. Currently, CoT descriptors which are used by BL2 are added as part of device tree. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Iff23cff843e5489fac18bcee5f5d6a71de5ad0d0
-
Sandrine Bailleux authored
-
- 09 Jul, 2020 3 commits
-
-
Manish V Badarkhe authored
Added a build option 'COT_DESC_IN_DTB' to create chain of trust at runtime using fconf. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I92b257ac4ece8bbf56f05a41d1e4056e2422ab89
-
Sandrine Bailleux authored
-
Manish V Badarkhe authored
Updated the CoT binding document to show chain of trust relationship with the help of 'authentication method' and 'authentication data' instead of showing content of certificate and fixed rendering issue while creating html page using this document. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ib48279cfe786d149ab69ddc711caa381a50f9e2b
-
- 08 Jul, 2020 1 commit
-
-
Sandrine Bailleux authored
-
- 07 Jul, 2020 3 commits
-
-
André Przywara authored
-
Varun Wadekar authored
This patch adds the IIDR value for GIC600-AE to the gicv3_is_gic600() helper function. This helps platforms supporting this version of the GIC600 interrupt controller to function with the generic GIC driver. Verified with tftf-validation test suite ******************************* Summary ******************************* > Test suite 'Framework Validation' Passed > Test suite 'Timer framework Validation' Passed ================================= Tests Skipped : 0 Tests Passed : 6 Tests Failed : 0 Tests Crashed : 0 Total tests : 6 ================================= NOTICE: Exiting tests. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I518ae7b56f7f372e374e453287d76ca370fc3574
-
Manish Pandey authored
-
- 06 Jul, 2020 1 commit
-
-
Abdellatif El Khlifi authored
This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
-
- 02 Jul, 2020 4 commits
-
-
Madhukar Pappireddy authored
-
Mark Dykes authored
* changes: stm32mp1: shared resources: apply registered configuration stm32mp1: shared resources: count GPIOZ bank pins stm32mp1: shared resources: define resource identifiers
-
Mark Dykes authored
-
Manish Pandey authored
-
- 01 Jul, 2020 3 commits
-
-
Lauren Wehrmeister authored
-
Lauren Wehrmeister authored
-
Sandrine Bailleux authored
Fix all external broken links reported by Sphinx linkcheck tool. This does not take care of broken cross-references between internal TF-A documentation files. These will be fixed in a future patch. Change-Id: I2a740a3ec0b688c14aad575a6c2ac71e72ce051e Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
-
- 30 Jun, 2020 3 commits
-
-
Manish Pandey authored
There were some links in the file "ras.rst" which were broken, this patch fixes all the broken links in this file. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I00cf080e9338af5786239a4843cb4c2e0cc9d99d
-
Sandrine Bailleux authored
-
Sandrine Bailleux authored
-
- 29 Jun, 2020 8 commits
-
-
Manish Pandey authored
-
Sami Mujawar authored
The TF-A firmware build system is capable of building on both Unix like and Windows host PCs. The commit ID 7ff088 "Enable MTE support" updated the Makefile to conditionally enable the MTE support if the AArch64 architecture revision was greater than 8.5. However, the Makefile changes were dependent on shell commands that are only available on unix shells, resulting in build failures on a Windows host PC. This patch fixes the Makefile by using a more portable approach for comparing the architecture revision. Change-Id: Icb56cbecd8af5b0b9056d105970ff4a6edd1755a Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
-
Mark Dykes authored
-
Mark Dykes authored
-
Manish V Badarkhe authored
Added assert in the code to check valid address of dtb information structure retrieved from fw_config device tree. This patch fixes coverity defect:360213. Also, removed conditional calling of "fconf_populate" as "fconf_populate" function already checks the validity of the device tree address received and go to panic in case of address is NULL. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ib83e4e84a95e2456a12c7a2bb3fe70461d882cba
-
André Przywara authored
-
Samuel Holland authored
The non-secure world has no business accessing the CPU power switches in the PRCM; those are handled by TF-A or the SCP. Only allow access to the clock control part of the PRCM. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I657b97f4ea8a0073448ad3343fbc66ba168ed89e
-
Masahiro Yamada authored
The .rela.dyn section is the same for BL2-AT-EL3, BL31, TSP. Move it to the common header file. I slightly changed the definition so that we can do "RELA_SECTION >RAM". It still produced equivalent elf images. Please note I got rid of '.' from the VMA field. Otherwise, if the end of previous .data section is not 8-byte aligned, it fails to link. aarch64-linux-gnu-ld.bfd: warning: changing start of section .rela.dyn by 4 bytes aarch64-linux-gnu-ld.bfd: warning: changing start of section .rela.dyn by 4 bytes aarch64-linux-gnu-ld.bfd: warning: changing start of section .rela.dyn by 4 bytes make: *** [Makefile:1071: build/qemu/release/bl31/bl31.elf] Error 1 Change-Id: Iba7422d99c0374d4d9e97e6fd47bae129dba5cc9 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
-
- 27 Jun, 2020 1 commit
-
-
Madhukar Pappireddy authored
This version corresponds to the following commit <7be250b> libfdt: Correct condition for reordering blocks Also, updated the Juno romlib jumptable with fdt APIs. Change-Id: Ib6d28c1aea81c2144a263958f0792cc4daea7a1f Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
-
- 26 Jun, 2020 7 commits
-
-
Manish Pandey authored
* changes: plat: marvell: armada: a8k: add OP-TEE OS MMU tables drivers: marvell: add support for mapping the entire LLC to SRAM plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms plat: marvell: armada: reduce memory size reserved for FIP image plat: marvell: armada: platform definitions cleanup plat: marvell: armada: a8k: check CCU window state before loading MSS BL2 drivers: marvell: add CCU driver API for window state checking drivers: marvell: align and extend llc macros plat: marvell: a8k: move address config of cp1/2 to BL2 plat: marvell: armada: re-enable BL32_BASE definition plat: marvell: a8k: extend includes to take advantage of the phy_porting_layer marvell: comphy: initialize common phy selector for AP mode marvell: comphy: update rx_training procedure plat: marvell: armada: configure amb for all CPs plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs
-
Andre Przywara authored
The plat_core_pos_by_mpidr() implementation for the Arm FPGA port has some issues, which leads to problems when matching GICv3 redistributors with cores: - The power domain tree was not taking multithreading into account, so we ended up with the wrong mapping between MPIDRs and core IDs. - Before even considering an MPIDR, we try to make sure Aff2 is 0. Unfortunately this is the cluster ID when the MT bit is set. - We mask off the MT bit in MPIDR, before basing decisions on it. - When detecting the MT bit, we are properly calculating the thread ID, but don't account for the shift in the core and cluster ID checks. Those problems lead to early rejections of MPIDRs values, in particular when called from the GIC code. As a result, CPU_ON for secondary cores was failing for most of the cores. Fix this by properly handling the MT bit in plat_core_pos_by_mpidr(), also pulling in FPGA_MAX_PE_PER_CPU when populating the power domain tree. Change-Id: I71b2255fc0d27bfe5806511df479ab38e4e33fc4 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-
Sandrine Bailleux authored
* changes: doc: Update arg usage for BL2 and BL31 setup functions doc: Update BL1 and BL2 boot flow plat/arm: Use only fw_config between bl2 and bl31
-
Manish V Badarkhe authored
Updated the porting guide for the usage of received arguments in BL2 and BL32 setup functions in case of Arm platform. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ia83a5607fed999819d25e49322b3bfb5db9425c0
-
Manish V Badarkhe authored
Updated the document for BL1 and BL2 boot flow to capture below changes made in FCONF 1. Loading of fw_config and tb_fw_config images by BL1. 2. Population of fw_config and tb_fw_config by BL2. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ifea5c61d520ff1de834c279ce1759b53448303ba
-
Manish V Badarkhe authored
Passed the address of fw_config instead of soc_fw_config as arg1 to BL31 from BL2 for ARM fvp platform. BL31 then retrieve load-address of other device trees from fw_config device tree. Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ib7e9581cd765d76111dcc3b7e0dafc12503c83c1
-
Sandrine Bailleux authored
* changes: doc: Update memory layout for firmware configuration area plat/arm: Increase size of firmware configuration area plat/arm: Load and populate fw_config and tb_fw_config fconf: Handle error from fconf_load_config plat/arm: Update the fw_config load call and populate it's information fconf: Allow fconf to load additional firmware configuration fconf: Clean confused naming between TB_FW and FW_CONFIG tbbr/dualroot: Add fw_config image in chain of trust cert_tool: Update cert_tool for fw_config image support fiptool: Add fw_config in FIP plat/arm: Rentroduce tb_fw_config device tree
-
- 25 Jun, 2020 1 commit
-
-
johpow01 authored
Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6
-