1. 06 May, 2014 2 commits
    • Dan Handley's avatar
      Make use of user/system includes more consistent · 35e98e55
      Dan Handley authored
      Make codebase consistent in its use of #include "" syntax for
      user includes and #include <> syntax for system includes.
      
      Fixes ARM-software/tf-issues#65
      
      Change-Id: If2f7c4885173b1fd05ac2cde5f1c8a07000c7a33
      35e98e55
    • Dan Handley's avatar
      Move FVP power driver to FVP platform · e8246c07
      Dan Handley authored
      Move the FVP power driver to a directory under the FVP platform
      port as this is not a generically usable driver.
      
      Change-Id: Ibc78bd88752eb3e3964336741488349ac345f4f0
      e8246c07
  2. 24 Apr, 2014 1 commit
    • Harry Liebel's avatar
      Enable secure memory support for FVPs · f2199d95
      Harry Liebel authored
      - Use the TrustZone controller on Base FVP to program DRAM access
        permissions. By default no access to DRAM is allowed if
        'secure memory' is enabled on the Base FVP.
      - The Foundation FVP does not have a TrustZone controller but instead
        has fixed access permissions.
      - Update FDTs for Linux to use timers at the correct security level.
      - Starting the FVPs with 'secure memory' disabled is also supported.
      
      Limitations:
      Virtio currently uses a reserved NSAID. This will be corrected in
      future FVP releases.
      
      Change-Id: I0b6c003a7b5982267815f62bcf6eb82aa4c50a31
      f2199d95
  3. 16 Apr, 2014 1 commit
    • Dan Handley's avatar
      Remove redundant code from bl1_plat_helpers.S · 9e1c4bd2
      Dan Handley authored
      Remove redundant code in plat_secondary_cold_boot_setup() in
      plat/fvp/aarch64/bl1_plat_helpers.S.
      
      Fixes ARM-software/tf-issues#136
      
      Change-Id: I98c0a46d95cfea33125e34e609c83dc2c97cd86e
      9e1c4bd2
  4. 15 Apr, 2014 2 commits
    • Andrew Thoelke's avatar
      Allocate single stacks for BL1 and BL2 · 2bf28e62
      Andrew Thoelke authored
      The BL images share common stack management code which provides
      one coherent and one cacheable stack for every CPU. BL1 and BL2
      just execute on the primary CPU during boot and do not require
      the additional CPU stacks. This patch provides separate stack
      support code for UP and MP images, substantially reducing the
      RAM usage for BL1 and BL2 for the FVP platform.
      
      This patch also provides macros for declaring stacks and
      calculating stack base addresses to improve consistency where
      this has to be done in the firmware.
      
      The stack allocation source files are now included via
      platform.mk rather than the common BLx makefiles. This allows
      each platform to select the appropriate MP/UP stack support
      for each BL image.
      
      Each platform makefile must be updated when including this
      commit.
      
      Fixes ARM-software/tf-issues#76
      
      Change-Id: Ia251f61b8148ffa73eae3f3711f57b1ffebfa632
      2bf28e62
    • Dan Handley's avatar
      Rename FVP "mmap" array to avoid name confusion · 67c78844
      Dan Handley authored
      Rename the array "mmap" in plat/fvp/aarch64/plat_common.c to
      "fvp_mmap", to avoid confusion with the array of the same name
      in lib/arch/aarch64/xlat_tables.c
      
      Fixes ARM-software/tf-issues#114
      
      Change-Id: I61478c0070aa52d5dcf5d85af2f353f56c060cfb
      67c78844
  5. 08 Apr, 2014 1 commit
    • Sandrine Bailleux's avatar
      Define frequency of system counter in platform code · 9e86490f
      Sandrine Bailleux authored
      BL3-1 architecture setup code programs the system counter frequency
      into the CNTFRQ_EL0 register. This frequency is defined by the
      platform, though. This patch introduces a new platform hook that
      the architecture setup code can call to retrieve this information.
      In the ARM FVP port, this returns the first entry of the frequency
      modes table from the memory mapped generic timer.
      
      All system counter setup code has been removed from BL1 as some
      platforms may not have initialized the system counters at this stage.
      The platform specific settings done exclusively in BL1 have been moved
      to BL3-1. In the ARM FVP port, this consists in enabling and
      initializing the System level generic timer. Also, the frequency change
      request in the counter control register has been set to 0 to make it
      explicit it's using the base frequency. The CNTCR_FCREQ() macro has been
      fixed in this context to give an entry number rather than a bitmask.
      
      In future, when support for firmware update is implemented, there
      is a case where BL1 platform specific code will need to program
      the counter frequency. This should be implemented at that time.
      
      This patch also updates the relevant documentation.
      
      It properly fixes ARM-software/tf-issues#24
      
      Change-Id: If95639b279f75d66ac0576c48a6614b5ccb0e84b
      9e86490f
  6. 26 Mar, 2014 1 commit
    • Andrew Thoelke's avatar
      Place assembler functions in separate sections · 0a30cf54
      Andrew Thoelke authored
      This extends the --gc-sections behaviour to the many assembler
      support functions in the firmware images by placing each function
      into its own code section. This is achieved by creating a 'func'
      macro used to declare each function label.
      
      Fixes ARM-software/tf-issues#80
      
      Change-Id: I301937b630add292d2dec6d2561a7fcfa6fec690
      0a30cf54
  7. 21 Mar, 2014 2 commits
    • Vikram Kanigiri's avatar
      Remove partially qualified asm helper functions · 6ba0b6d6
      Vikram Kanigiri authored
      Each ARM Trusted Firmware image should know in which EL it is running
      and it should use the corresponding register directly instead of reading
      currentEL and knowing which asm register to read/write
      
      Change-Id: Ief35630190b6f07c8fbb7ba6cb20db308f002945
      6ba0b6d6
    • Vikram Kanigiri's avatar
      Fix the disable_mmu code · 5132060c
      Vikram Kanigiri authored
      Remove the hard coding of all the MMU related registers with 0 and disable MMU
      by clearing the M and C bit in SCTLR_ELx
      
      Change-Id: I4a0b1bb14a604734b74c32eb31315d8504a7b8d8
      5132060c
  8. 10 Mar, 2014 1 commit
  9. 05 Mar, 2014 1 commit
  10. 20 Feb, 2014 2 commits
    • Achin Gupta's avatar
      Add Test Secure Payload (BL3-2) image · 7c88f3f6
      Achin Gupta authored
      
      
      This patch adds a simple TSP as the BL3-2 image. The secure payload
      executes in S-EL1. It paves the way for the addition of the TSP
      dispatcher runtime service to BL3-1. The TSP and the dispatcher service
      will serve as an example of the runtime firmware's ability to toggle
      execution between the non-secure and secure states in response to SMC
      request from the non-secure state.  The TSP will be replaced by a
      Trusted OS in a real system.
      
      The TSP also exports a set of handlers which should be called in
      response to a PSCI power management event e.g a cpu being suspended or
      turned off. For now it runs out of Secure DRAM on the ARM FVP port and
      will be moved to Secure SRAM later. The default translation table setup
      code assumes that the caller is executing out of secure SRAM. Hence the
      TSP exports its own translation table setup function.
      
      The TSP only services Fast SMCs, is non-reentrant and non-interruptible.
      It does arithmetic operations on two sets of four operands, one set
      supplied by the non-secure client, and the other supplied by the TSP
      dispatcher in EL3. It returns the result according to the Secure Monitor
      Calling convention standard.
      
      This TSP has two functional entry points:
      
      - An initial, one-time entry point through which the TSP is initialized
        and prepares for receiving further requests from secure
        monitor/dispatcher
      
      - A fast SMC service entry point through which the TSP dispatcher
        requests secure services on behalf of the non-secure client
      
      Change-Id: I24377df53399307e2560a025eb2c82ce98ab3931
      Co-authored-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      7c88f3f6
    • Achin Gupta's avatar
      Factor out translation table setup in ARM FVP port · a0cd989d
      Achin Gupta authored
      This patch factors out the ARM FVP specific code to create MMU
      translation tables so that it is possible for a boot loader stage to
      create a different set of tables instead of using the default ones.
      The default translation tables are created with the assumption that
      the calling boot loader stage executes out of secure SRAM. This might
      not be true for the BL3_2 stage in the future.
      
      A boot loader stage can define the `fill_xlation_tables()` function as
      per its requirements. It returns a reference to the level 1
      translation table which is used by the common platform code to setup
      the TTBR_EL3.
      
      This patch is a temporary solution before a larger rework of
      translation table creation logic is introduced.
      
      Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6
      a0cd989d
  11. 17 Feb, 2014 2 commits
    • Jeenu Viswambharan's avatar
      Move translation tables into separate section · 74cbb839
      Jeenu Viswambharan authored
      This patch moves the translation tables into their own section. This
      saves space that would otherwise have been lost in padding due to page
      table alignment constraints. The BL31 and BL32 bases have been
      consequently adjusted.
      
      Change-Id: Ibd65ae8a5ce4c4ea9a71a794c95bbff40dc63e65
      74cbb839
    • James Morrissey's avatar
      Fix asserts appearing in release builds · 40a6f647
      James Morrissey authored
      Also fix warnings generated in release builds when assert code
      is absent.
      
      Change-Id: I45b9173d3888f9e93e98eb5b4fdc06727ba5cbf4
      40a6f647
  12. 20 Jan, 2014 1 commit
  13. 17 Jan, 2014 3 commits
    • Jeenu Viswambharan's avatar
      Change comments in assembler files to help ctags · 3a4cae05
      Jeenu Viswambharan authored
      Ctags seem to have a problem with generating tags for assembler symbols
      when a comment immediately follows an assembly label.
      
      This patch inserts a single space character between the label
      definition and the following comments to help ctags.
      
      The patch is generated by the command:
      
        git ls-files -- \*.S | xargs sed -i 's/^\([^:]\+\):;/\1: ;/1'
      
      Change-Id: If7a3c9d0f51207ea033cc8b8e1b34acaa0926475
      3a4cae05
    • Dan Handley's avatar
      Update year in copyright text to 2014 · e83b0cad
      Dan Handley authored
      Change-Id: Ic7fb61aabae1d515b9e6baf3dd003807ff42da60
      e83b0cad
    • Ian Spray's avatar
      Move GIC setup to a separate file · 8468739c
      Ian Spray authored
      GIC setup code which used to be in bl31_plat_setup.c is now in fvp_gic.c
      to simplify future changes to other bootloader stages.  This patch moves
      code from bl31_plat_setup.c to fvp_gic.c, simplifies the include file
      list for bl31_plat_setup.c, moves GIC declarations from the bl31.h header
      file into the platform.h, and reworks files according to coding style
      guide.
      
      Change-Id: I48d82a4ba33e7114dcc88f9ca98767a06cf8f417
      8468739c
  14. 05 Dec, 2013 2 commits
    • Dan Handley's avatar
      Enable third party contributions · ab2d31ed
      Dan Handley authored
      - Add instructions for contributing to ARM Trusted Firmware.
      
      - Update copyright text in all files to acknowledge contributors.
      
      Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5
      ab2d31ed
    • Sandrine Bailleux's avatar
      Various improvements/cleanups on the linker scripts · 8d69a03f
      Sandrine Bailleux authored
        - Check at link-time that bootloader images will fit in memory
          at run time and that they won't overlap each other.
        - Remove text and rodata orphan sections.
        - Define new linker symbols to remove the need for platform setup
          code to know the order of sections.
        - Reduce the size of the raw binary images by cutting some sections
          out of the disk image and allocating them at load time, whenever
          possible.
        - Rework alignment constraints on sections.
        - Remove unused linker symbols.
        - Homogenize linker symbols names across all BLs.
        - Add some comments in the linker scripts.
      
      Change-Id: I47a328af0ccc7c8ab47fcc0dc6e7dd26160610b9
      8d69a03f
  15. 27 Nov, 2013 1 commit
  16. 14 Nov, 2013 2 commits
  17. 25 Oct, 2013 1 commit