- 20 Apr, 2021 2 commits
-
-
Lad Prabhakar authored
Add support to identify HopeRun HiHope RZ/G2H board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I6b28350ef50595fea9a1b1b7353fcabaeb935970
-
Lad Prabhakar authored
Switch using common ddr driver code from renesas/common/ddr directory for RZ/G2M SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I807dcb0bc5186bd32bc1c577945d28634bb10e1f
-
- 13 Jan, 2021 2 commits
-
-
Biju Das authored
Add DT node support for channel 0 where physical memory is split between 32bit space and 64bit space. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I99a18dbb14cdb54100a836c16445242e430794e3
-
Biju Das authored
The HiHope RZ/G2M board from HopeRun consists of main board (HopeRun HiHope RZ/G2M main board) and sub board(HopeRun HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits below the HiHope RZ/G2M main board. This patch adds the required board support to boot HopeRun HiHope RZ/G2M board. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I3ed55aa4a2cc5c9d9cd6440e087bcd93186520c7
-
- 28 Apr, 2020 1 commit
-
-
Marek Vasut authored
Make sure the string generated in unsigned_num_print() is zero-terminated. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ic0ac1ebca255002522159a9152ab41991f043d05
-
- 15 Feb, 2020 1 commit
-
-
Toshiyuki Ogasahara authored
This patch changes the destination address of BL31 and BL32 From fixed address for getting from the each certificates. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream rework Change-Id: Ide11776feff25e6fdd55ab28503a15b658b2e0d5
-
- 28 Jan, 2020 1 commit
-
-
Madhukar Pappireddy authored
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
-
- 15 Jan, 2020 1 commit
-
-
Marek Vasut authored
Add missing #address-cells and #size-cells into generated DT, otherwise the DT is invalid. While the parsers thus far handled this correctly via various fallbacks, this is not applicable in the long run, so fix this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ic808a3b27b93e5258ec1a19acc3d593e53625c15
-
- 19 Nov, 2019 1 commit
-
-
Justin Chadwell authored
Variable shadowing is, according to the C standard, permitted and valid behaviour. However, allowing a local variable to take the same name as a global one can cause confusion and can make refactoring and bug hunting more difficult. This patch moves -Wshadow from WARNING2 into the general warning group so it is always used. It also fixes all warnings that this introduces by simply renaming the local variable to a new name Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
- 16 Aug, 2019 1 commit
-
-
Marek Vasut authored
Rename RCAR_PRODUCT_* to PRR_PRODUCT_* and drop the duplicate RCAR_PRODUCT_* macro. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I6b2789790b85edb79c026f0860d70f323d113d96
-
- 13 Jun, 2019 1 commit
-
-
Marek Vasut authored
Convert the R-Car Gen3 platform and both SCIF and Log drivers to multi-console API. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I18556973937d150b60453f9150d54ee612571e35
-
- 02 Apr, 2019 3 commits
-
-
Valentine Barshak authored
Add R-Car V3M support. This is based on the original V3M support patch for Yocto v2.23.1 by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> --- Marek: Update on top of mainline ATF/master
-
Marek Vasut authored
Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code will be added separately. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Print the DRAM bank size in MiB instead of GiB in case the bank size is smaller than 1 GiB. This prevents printing zeroes on systems with small DRAM sizes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
- 26 Mar, 2019 1 commit
-
-
Marek Vasut authored
The M3W ULCB board has 2 GiB of DRAM, set it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
- 04 Mar, 2019 1 commit
-
-
Marek Vasut authored
Add support for the M3W 3.0 SoC and synchronize the upstream ATF with Renesas downstream ATF release v2.0.1. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
- 08 Jan, 2019 6 commits
-
-
Marek Vasut authored
Add code to determine the platform timer frequency and configure the generic timer accordingly early in BL2. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Disable the IPMMU PV0 cache on E3 rev. 1.x . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Add support for R-Car E3 silicon rev. 1.1 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Add missing TARGET_NAME for the case where RCAR_LSI is set to AUTO, which is platform auto-detection. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable BL2 area. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Replace foo_t with struct foo. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
- 04 Jan, 2019 1 commit
-
-
Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 06 Dec, 2018 9 commits
-
-
Marek Vasut authored
Generate a /reserved-memory node for FCNL in the DT passed to subsequent stages, so they will know how the FCNL is configured. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Generate /compatible string for the platform, so that the subsequent stages know which platform they are running on. This could be useful when ie. building U-Boot that contains DTs for multiple platforms and can thus decide on which platform it is running. This would ultimately allow single bootloader binary for all Gen3 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Pass DTB containing DRAM layout from BL2 to BL33 via register x3, so that the BL33 can simply consume it and get accurate DRAM layout info. BL33 is in most usecases U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Use array of start-size tuples for the DRAM banks and call single function which iterates over this array to report the DRAM info. This is in preparation for expanding this to generate FDT for the next stage. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Print the DRAM configuration only after the DRAM was initialized. This will be useful when deduplicating code populating FDT passed to U-Boot, since it will contain the same macros as bl2_advertise_dram_size(). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Make the DRAM configuration debug print consistent for all supported SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
There is nothing preventing H3 older than v3.0 from printing the DRAM configuration, just like v3.0 and newer. Drop the check and let all H3 revisions print DRAM configuration in BL2. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
RCAR_DRAM_DDR3L_MEMCONF = 2 means E3 with 1GBx4 memory configuration. Add debug print for this configuration for completeness sake. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
Marek Vasut authored
Just move the DRAM layout information into separate function, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
-
- 17 Oct, 2018 1 commit
-
-
Jorge Ramirez-Ortiz authored
Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
-