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[IPL/QoS]
- Update M3 Ver.3.0 QoS setting rev.0.04.
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I798401f417df6a352d94311ea07a1e96ba562f6a

Clean up the DDR B header files and remove checkpatch errors.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9648ef5511df299688fd5284513812d32a1f8064

Fix as many line-over-80s as possible. There are still a few remaining,
which would need further refactoring.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I7225d9fab658d05e3315d8c3fa3c9f3bbb1ab40d

Address more checkpatch CHECKs and ERRORs, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ife682288cef3afa860571b2aca647c9ffe936125

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ifda28578f326b1d4518560384d50ae98806db26e

Do basic automated checkpatch fixes on the ddr_b, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie401ec049a05d2c4c8044749994391adea171679

The ddr_a and ddr_b register macros are the same for the most part,
unify them into a single header.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I8f55d6d779837215339ac0010e8c8ab5f6748d75

Do minor coding style changes to the common DDR init code to make it
checkpatch compliant and move macros out into rcar_def.h.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I67eadf8099e4ff8702105c9e07b13f308d9dbe3d

This patch fixes an issue when secure world timing information
can be leaked because Secure Cycle Counter is not disabled.
For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD
bit on CPU cold/warm boot.
For the earlier architectures PMCR_EL0 register is saved/restored
on secure world entry/exit from/to Non-secure state, and cycle
counting gets disabled by setting PMCR_EL0.DP bit.
'include\aarch64\arch.h' header file was tided up and new
ARMv8.5-PMU related definitions were added.

Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

This patch adds support for Corstone-700 foundation IP, which integrates
both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible
subsystem.
This is an example implementation of Corstone-700 IP host firmware.

Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as
bringing Host out RESET. Host will start execution directly from BL32 and
then will jump to Linux.

It is an initial port and additional features are expected to be added
later.

Change-Id: I7b5c0278243d574284b777b2408375d007a7736e
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

ISB instruction was removed from the N1 1043202 Errata Workaround [1], this
fix is adding the ISB instruction back in.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I74eac7f6ad38991c36d423ad6aa44558033ad388

Driver will calculate DDR size instead of using hardcoded value
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde

Currently, console drivers prepend '\r' to '\n' by themselves. This is
common enough to be supported in the framework.

Add a new flag, CONSOLE_FLAG_TRANSLATE_CRLF. A driver can set this
flag to ask the framework to transform LF into CRLF instead of doing
it by itself.

Change-Id: I4f5c5887591bc0a8749a105abe62b6562eaf503b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

To provide glitchless clock to downstream logic even if clock toggles
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1

GCC diagnostics were added to ignore array boundaries, instead
of ignoring GCC warning current code will check for array boundaries
and perform and array update only for valid elements.

Resolves: `CID 246574` `CID 246710` `CID 246651`
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I7530ecf7a1707351c6ee87e90cc3d33574088f57

SMMUv3 driver functions which are called from BL1 and BL31
currently use counter-based poll method for testing status
bits. Adding Delay Timer driver to BL1 and BL31 is required
for timeout-based implementation using timer delay functions
for SMMU and other drivers.
This patch adds new function `fvp_timer_init()` which
initialises either System level generic or SP804 timer based on
FVP_USE_SP804_TIMER build flag.
In BL2U `bl2u_early_platform_setup()` function the call to
`arm_bl2u_early_platform_setup()` (which calls
`generic_delay_timer_init()` ignoring FVP_USE_SP804_TIMER flag),
is replaced with `arm_console_boot_init()` and `fvp_timer_init()`.

Change-Id: Ifd8dcebf4019e877b9bc5641551deef77a44c0d1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Rename RCAR_PRODUCT_* to PRR_PRODUCT_* and drop the duplicate
RCAR_PRODUCT_* macro.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I6b2789790b85edb79c026f0860d70f323d113d96

Pull out the PRR_* macros into rcar_def.h and remove multiple copies of
it. Now that there are still RCAR_* macros in rcar_def.h too and they
have the exact same meaning as the PRR_* macros, but that's for another
patch.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Icb7f61b971b1a23102bd1b9f58cda580660a55fc

The valgrind checks for cert_create have not been run in a long while -
as such there are a few memory leaks present. This patch fixes a few of
the major ones reported by valgrind. However, a few do remain.

Change-Id: Iab002fb2b0090043287d43fb54a4d18928c2ed85
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

This patch fixes FVP_Base_AEMv8A model hang issue with
ARMv8.4+ with cache modelling enabled configuration.
Incorrect L1 cache flush operation to PoU, using CLIDR_EL1
LoUIS field, which is required by the architecture to be
zero for ARMv8.4-A with ARMv8.4-S2FWB feature is replaced
with L1 to L2 and L2 to L3 (if L3 is present) cache flushes.
FVP_Base_AEMv8A model can be configured with L3 enabled by
setting `cluster0.l3cache-size` and `cluster1.l3cache-size`
to non-zero values, and presence of L3 is checked in
`aem_generic_core_pwr_dwn` function by reading
CLIDR_EL1.Ctype3 field value.

Change-Id: If3de3d4eb5ed409e5b4ccdbc2fe6d5a01894a9af
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

* changes:
  Juno: Use shared mbedtls heap between bl1 and bl2
  Juno: add basic support for dynamic config

This patch updates all Tegra platforms to use the new multi console API.

Change-Id: I27c0c7830a86e26491dea9991a689f0b01e4dbf0
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Julius Werner <jwerner@chromium.org>

* changes:
  rockchip: rk3399: store actual debug uart information on suspend
  rockchip: move dt-coreboot uart distinction into param handling code
  rockchip: make uart baudrate configurable
  rockchip: px30: add uart5 as option for serial output

This patch modifies crash reporting for AArch64 to provide
aligned output of register dump and GIC registers.

Change-Id: I8743bf1d2d6d56086e735df43785ef28051c5fc3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Increase calibration delay, fix ddrio control config & nonsecure region
limit
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ibca3c247a3ad5104176ca9057d29755599f13c9b