- 11 Feb, 2019 1 commit
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Ryan Grachek authored
There exists a third DMA controller on the hi3660 SoC called the IOMCU DMAC. This controller is used by peripherals like SPI2 and UART3. Initialize channels 4-7 as non-secure, while 0-3 remain reserved and secure. Signed-off-by: Ryan Grachek <ryan@edited.us>
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- 01 Feb, 2019 2 commits
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Antonio Nino Diaz authored
Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Many parts of the code were duplicating symbols that are defined in include/common/bl_common.h. It is better to only use the definitions in this header. As all the symbols refer to virtual addresses, they have to be uintptr_t, not unsigned long. This has also been fixed in bl_common.h. Change-Id: I204081af78326ced03fb05f69846f229d324c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 31 Jan, 2019 1 commit
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Ryan Grachek authored
Channel 0 is used to communicate with LPM3, a coprocessor for power management. Leave it as secure. Signed-off-by: Ryan Grachek <ryan@edited.us>
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- 15 Jan, 2019 1 commit
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Antonio Nino Diaz authored
The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for platforms that may need to access them. Change-Id: Ifd1880f855ddafcb3bfcaf1ed4a4e0f121eda174 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 10 Jan, 2019 2 commits
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Joel Hutton authored
Change-Id: I7194a9a5f0e41308eb3242d20c0d3434f72da591 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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Joel Hutton authored
It is cleaner to use the same number of tables regardless of whether OP-TEE is used or not. This doesn't result in a significant memory usage increase. Change-Id: I38bcaa3f2f197c0a352153117592749f189a265c Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 10 Dec, 2018 1 commit
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Yann Gautier authored
This is used as a table index, and already compared with an unsigned int: block_dev_count. Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 29 Nov, 2018 1 commit
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Ryan Grachek authored
This is needed to utilize the DMA controller on the hikey960 Signed-off-by: Ryan Grachek <ryan@edited.us>
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- 08 Nov, 2018 2 commits
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Jerome Forissier authored
Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1. Enables building with ERROR_DEPRECATED=1. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 01 Nov, 2018 1 commit
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Antonio Nino Diaz authored
The macro EL_IMPLEMENTED() has been deprecated in favour of the new function el_implemented(). Change-Id: Ic9b1b81480b5e019b50a050e8c1a199991bf0ca9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 25 Oct, 2018 1 commit
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Antonio Nino Diaz authored
Even though at this point plat_crash_console_flush is optional, it will stop being optional in a following patch. The console driver of warp7 doesn't support flush, so the implementation is a placeholder. TI had ``plat_crash_console_init`` and ``plat_crash_console_putc``, but they weren't global so they weren't actually used. Also, they were calling the wrong functions. imx8_helpers.S only has placeholders for all of the functions. Change-Id: I8d17bbf37c7dad74e134c61ceb92acb9af497718 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Migrate to new GIC interfaces. - Remove unused bl1_init_bl2_mem_layout(). - Migrate to bl31_early_platform_setup2(). - Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE. - Remove references to removed build options. - Update Makefile paths. Change-Id: I583fd893555e6535f32d87ed67bbae430b8e6afe Tested-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 26 Sep, 2018 1 commit
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Haojian Zhuang authored
plat/hisilicon/hikey960/include/plat_macros.S:19:55: error: unexpected token in '.asciz' directive .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" " Offset:\t\t\tvalue\n" ^ Makefile:720: recipe for target 'build/hikey960/debug/bl1/cortex_a53.o' failed make: *** [build/hikey960/debug/bl1/cortex_a53.o] Error 1 Merge the two lines into one. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 09 Sep, 2018 1 commit
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Teddy Reed authored
This patch adds experimental support for TBB to the HiKey960 board. To build and test with TBB modify the uefi-tools project platforms.config +ATF_BUILDFLAGS=TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 SAVE_KEYS=1 \ MBEDTLS_DIR=./mbedtls Signed-off-by: Teddy Reed <teddy@casualhacking.io>
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- 27 Jul, 2018 1 commit
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Kaihua Zhong authored
GPIO_089 connects to PCIE_PERST_N. It needs to be configured as output low. Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 20 Jul, 2018 1 commit
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Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 28 Mar, 2018 1 commit
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Haojian Zhuang authored
If system is still accessing storage device, reboot operation may cause data broken. So add the flush and delay operation before system reset. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 27 Mar, 2018 1 commit
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Joel Hutton authored
Void pointers have been used to access linker symbols, by declaring an extern pointer, then taking the address of it. This limits symbols values to aligned pointer values. To remove this restriction an IMPORT_SYM macro has been introduced, which declares it as a char pointer and casts it to the required type. Change-Id: I89877fc3b13ed311817bb8ba79d4872b89bfd3b0 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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- 26 Mar, 2018 1 commit
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Jonathan Wright authored
Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7. Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
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- 06 Mar, 2018 1 commit
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Haojian Zhuang authored
plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c:290:20: error: unused function 'hisi_pdc_set_intmask' [-Werror,-Wunused-function] static inline void hisi_pdc_set_intmask(void *pdc_base_addr, ^ 1 error generated. Makefile:605: recipe for target 'build/hikey960/release/bl31/hisi_pwrc.o' failed make: *** [build/hikey960/release/bl31/hisi_pwrc.o] Error 1 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 05 Mar, 2018 6 commits
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Haojian Zhuang authored
Create hikey960_bl_common.c to store duplication initialization code in both BL1 and BL2. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
It's unnecessary to call platform driver initialization in image load driver. We could make bl2_platform_setup() to executing just before SCP_BL2 by setting flag IMAGE_ATTRIB_PLAT_SETUP. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Since non-TF ROM is used in HiKey960 platform (Hisilicon Hi3660 SoC), replace BL1 by BL2_EL3 in normal boot mode. When flush images in recovery mode, keep to use BL1. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Since LOAD_IMAGE_V2 is always enabled in HiKey960 platform. Drop LOAD_IMAGE v1 to simplify code. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
MAP_TSP_MEM could be either in SRAM or DRAM. When MAP_TSP_MEM is in DRAM, it's overlapped with MAP_DDR. Since TSP_MEM is always configured in DRAM case, it means MAP_OPTEE_PAGEABLE is always disabled. Just remove it. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
The main difference between HiKey960 v1 hardware and HiKey960 v2 hardware is on UART console. But the function of detecting boardid dumps message before console ready. So fix it by removing those messages. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 27 Feb, 2018 1 commit
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David Cunado authored
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
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- 17 Feb, 2018 1 commit
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Haojian Zhuang authored
Avoid hardcode on uart port. The uart port could be auto detected on HiKey960 platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 07 Feb, 2018 1 commit
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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- 01 Feb, 2018 2 commits
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Masahiro Yamada authored
In the next commit, I need the image name in lowercase because output files are generally named in lowercase. Unfortunately, TOOL_ADD_IMG takes the first argument in uppercase since we generally use uppercase Make variables. make_helpers/build_macros.mk provides 'uppercase' macro to convert a string into uppercase, but 'lowercase' does not exist. We can implement it if we like, but it would be more straightforward to change the argument of TOOL_ADD_IMG. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Now FIP_ADD_IMG takes care of both fiptool and cert_create symmetrically. Rename it so that it matches the behavior. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 22 Jan, 2018 1 commit
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Leo Yan authored
When some interrupts are configured as group 0 in GICv2, these interrupts trigger FIQ signal; this results in the Linux kernel panic by reporting log: "Bad mode in FIQ handler detected on CPU0, code 0x00000000 -- Unknown/Uncategorized". Unfortunately from kernel side it has no permission to read the GIC register for group 0 interrupts so we have no chance to get to know which interrupt is configured as secure interrupt and cause the kernel panic. For upper reason, this commit enables FIQ exception handling for SPD_none case. If the system has not enabled SPD the FIQ interrupt is trapped into EL3 and the FIQ handler can report the interrupt number so we can easily narrow down which FIQ introduce unexpected interrupt. After enable SPD we can rely on SPD interrupt route model to handle FIQ. Signed-off-by: Leo Yan <leo.yan@linaro.org>
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- 16 Jan, 2018 2 commits
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Leo Yan authored
At early time, the CPU CA73 retention state has been supported on Hikey960. Later we found the system has the hang issue and for resolving this issue Hisilicon released new MCU firmware, but unfortunately the new MCU firmware has side effect and results in the CA73 CPU cannot really enter retention state and roll back to WFI state. After discussion we cannot see the possibility to enable CA73 retention state anymore on Hikey960, based on this conclusion we should remove this state supporting from ARM-TF and roll back to WFI state only. We will commit one patch to remove CA73 CPU retention state in kernel DT binding as well. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Kevin Wang <jean.wangtao@linaro.org> Cc: Vincent Guittot <vincent.guittot@linaro.org> Signed-off-by: Leo Yan <leo.yan@linaro.org>
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Leo Yan authored
This reverts commit fdae60b6. The commit fdae60b6 changed the parameter encoding for the hikey960. However that implies a DT change in the kernel side. After submitting the DT change for upstreaming, the backward compatibility issue and the interface change raise some concerns from the Linux community about the issues related to kernel <-> ATF alignment. There is no way to detect a mis-alignment of those without a deep knowledge of the ATF and the kernel. Furthermore, the failing calls to PSCI in the idle path (because of bad parameters), will lead to busy looping, implying: thermal issues and extra energy consumption. In regard of the Linux community concerns, the potential issues when the ATF and the kernel are not aligned, it is preferable to revert the commit. Cc: Vincent Guittot <vincent.guittot@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Kevin Wang <jean.wangtao@linaro.org> Co-authored-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Leo Yan <leo.yan@linaro.org>
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- 09 Jan, 2018 1 commit
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Kaihua Zhong authored
Set IOC_AO_IOMG_033 function from GPIO213 to PCIE_CLKREQ_N bit[0-2]: 000: GPIO_213; 001: PCIE_CLKREQ_N; 010: GPIO_018_SH; 100: GPIO_014_SE; 110: FAC_TEST24; 111: FAC_TEST24; bit[3-31]: reserved Signed-off-by: Guangtao Zhang <zhangguangtao@hisilicon.com> Tested-by: Yao Chen <chenyao11@huawei.com> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 18 Dec, 2017 1 commit
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Haojian Zhuang authored
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 06 Dec, 2017 1 commit
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Leo Yan authored
ARM Power State Coordination Interface (ARM DEN 0022D) chapter 6.5 "Recommended StateID Encoding" defines the state ID which can be used by platforms. The recommended power states can be presented by below values; and it divides into three fields, every field has 4 bits to present power states corresponding to core level, cluster level and system level. 0: Run 1: Standby 2: Retention 3: Powerdown This commit changes to use upper recommended power states definition on Hikey960; and changes the power state validate function to check the power state passed from kernel side. Signed-off-by: Leo Yan <leo.yan@linaro.org>
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