Skip to content

GitLab

Switch branch/tag
  1. 03 Oct, 2018 3 commits
  3. 02 Oct, 2018 1 commit
    • Antonio Nino Diaz's avatar
      plat/arm: Remove option ARM_BOARD_OPTIMISE_MEM · c0740e4f
      Antonio Nino Diaz authored 
      

This option makes it hard to optimize the memory definitions of all Arm
platforms because any change in the common defines must work in all of
them. The best thing to do is to remove it and move the definition to
each platform's header.

FVP, SGI and SGM were using the definitions in board_arm_def.h. The
definitions have been copied to each platform's platform_def.h. Juno
was already using the ones in platform_def.h, so there have been no
changes.

Change-Id: I9aecd11bbc72a3d0d7aad1ef9934d8df21dcfaf2
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c0740e4f
  5. 28 Sep, 2018 3 commits
  7. 26 Sep, 2018 1 commit
  9. 24 Sep, 2018 1 commit
  11. 18 Sep, 2018 1 commit
  13. 10 Sep, 2018 1 commit
  15. 07 Sep, 2018 5 commits
    • Sathees Balya's avatar
      juno: Revert FWU update detect mechanism · 4da6f6cd
      Sathees Balya authored 
      The patch 7b56928a

 unified the FWU mechanism on FVP and Juno
platforms due to issues with MCC firmware not preserving the
NVFLAGS. With MCCv150 firmware, this issue is resolved. Also
writing to the NOR flash while executing from the same flash
in Bypass mode had some stability issues. Hence, since the
MCC firmware issue is resolved, this patch reverts to the
NVFLAGS mechanism to detect FWU. Also, with the introduction
of SDS (Shared Data Structure) by the SCP, the reset syndrome
needs to queried from the appropriate SDS field.

Change-Id: If9c08f1afaaa4fcf197f3186887068103855f554
Signed-off-by: default avatarSathees Balya <sathees.balya@arm.com>
Signed-off-by: default avatarSoby Mathew <Soby.Mathew@arm.com>
      4da6f6cd
    • Alexei Fedorov's avatar
      ARM Platforms:Enable non-secure access to UART1 · 2431d00f
      Alexei Fedorov authored 
      

Adds an undocumented build option that enables non-secure access to
the PL011 UART1.
This allows a custom build where the UART can be used as a serial debug
port for WinDbg (or other debugger) connection.

This option is not documented in the user guide, as it is provided as a
convenience for Windows debugging, and not intended for general use.
In particular, enabling non-secure access to the UART might allow
a denial of service attack!

Change-Id: I4cd7d59c2cac897cc654ab5e1188ff031114ed3c
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: default avatarEvan Lloyd <evan.lloyd@arm.com>
      2431d00f
    • John Tsichritzis's avatar
      Add cache flush after BL1 writes heap info to DTB · 63cc2658
      John Tsichritzis authored 
      

A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we
ensure that the heap info written to the DTB always gets written back to
memory.  Hence, sharing this info with other images is guaranteed.

Change-Id: I0faada31fe7a83854cd5e2cf277ba519e3f050d5
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      63cc2658
    • John Tsichritzis's avatar
      Additional runtime check for DTB presence in BL2 · a606031e
      John Tsichritzis authored 
      

In Mbed TLS shared heap code, an additional sanity check is introduced
in BL2. Currently, when BL2 shares heap with BL1, it expects the heap
info to be found in the DTB. If for any reason the DTB is missing, BL2
cannot have the heap address and, hence, Mbed TLS cannot proceed. So,
BL2 cannot continue executing and it will eventually crash.  With this
change we ensure that if the DTB is missing BL2 will panic() instead of
having an unpredictable crash.

Change-Id: I3045ae43e54b7fe53f23e7c2d4d00e3477b6a446
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      a606031e
    • John Tsichritzis's avatar
      Slight improvements in Mbed TLS shared heap helpers · 7af2dd2e
      John Tsichritzis authored 
      

This patch, firstly, makes the error messages consistent to how printed
strings are usually formatted. Secondly, it removes an unnecessary #if
directive.

Change-Id: Idbb8ef0070562634766b683ac65f8160c9d109e6
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      7af2dd2e
  17. 04 Sep, 2018 3 commits
  19. 30 Aug, 2018 2 commits
  21. 23 Aug, 2018 1 commit
  23. 22 Aug, 2018 1 commit
  25. 21 Aug, 2018 1 commit
  27. 20 Aug, 2018 1 commit
  29. 10 Aug, 2018 1 commit
  31. 06 Aug, 2018 1 commit
  33. 03 Aug, 2018 7 commits
  35. 01 Aug, 2018 1 commit
    • Daniel Boulby's avatar
      Fix build for SEPARATE_CODE_AND_RODATA=0 · 2ecaafd2
      Daniel Boulby authored 
      

TF won't build since no memory region is specified
for when SEPARATE_CODE_AND_RODATA=0 it still relies on
the ARM_MAP_BL_RO_DATA region which is never defined for
this case. Create memory region combining code and RO data for
when the build flag SEPARATE_CODE_AND_RODATA=0 to fix this

Change-Id: I6c129eb0833497710cce55e76b8908ce03e0a638
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      2ecaafd2
  37. 26 Jul, 2018 5 commits
    • Sughosh Ganu's avatar
      RAS: SGI: Add flags needed to build components for RAS feature · f29d1828
      Sughosh Ganu authored 
      

Add the various flags that are required to build the components needed
to enable the RAS feature on SGI575 platform. By default, all flags
are set to 0, disabling building of all corresponding components.

Change-Id: I7f8536fba895043ef6e397cc33ac9126cb572132
Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      f29d1828
    • Sughosh Ganu's avatar
      RAS: SGI575: Add platform specific RAS changes · 167dae4d
      Sughosh Ganu authored 
      

Add platform specific changes needed to add support for the RAS
feature on SGI575 platform, including adding a mapping for the
CPER buffer being used on SGI575 platform.

Change-Id: I01a982e283609b5c48661307906346fa2738a43b
Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      167dae4d
    • Sughosh Ganu's avatar
      RAS: SGI: Add platform handler for RAS interrupts · 485fc954
      Sughosh Ganu authored 
      

Add a platform specific handler for RAS interrupts and configure the
platform RAS interrupts for EL3 handling. The interrupt handler passes
control to StandaloneMM code executing in S-EL0, which populates the
CPER buffer with relevant error information. The handler subsequently
invokes the SDEI client which processes the information in the error
information in the CPER buffer. The helper functions
plat_sgi_get_ras_ev_map and plat_sgi_get_ras_ev_map_size would be
defined for sgi platforms in the subsequent patch, which adds sgi575
specific RAS changes.

Change-Id: I490f16c15d9917ac40bdc0441659b92380108d63
Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      485fc954
    • Sughosh Ganu's avatar
      SPM: SGI: Map memory allocated for secure partitions · d9523919
      Sughosh Ganu authored 
      

The secure partition manager reserves chunks of memory which are used
for the S-EL0 StandaloneMM image and the buffers required for
communication between the Non-Secure world with the StandaloneMM
image. Add the memory chunks to relevant arrays for mapping the
regions of memory with corresponding attributes.

Change-Id: If371d1afee0a50ca7cacd55e16aeaca949d5062b
Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      d9523919
    • Sughosh Ganu's avatar
      ARM platforms: Allow board specific definition of SP stack base · 2e4a509d
      Sughosh Ganu authored 
      

The SGI platforms need to allocate memory for CPER buffers. These
platform buffers would be placed between the shared reserved memory
and the per cpu stack memory, thus the need to redefine stack base
pointer for these platforms. This patch allows each board in ARM
platform to define the PLAT_SP_IMAGE_STACK_BASE.

Change-Id: Ib5465448b860ab7ab0f645f7cb278a67acce7be9
Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      2e4a509d