- 04 Jan, 2021 1 commit
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Kalyani Akula authored
This patch adds new zynqmp-pm api to provide read/write access to CSU or PMU global registers. Signed-off-by: Kalyani Akula <kalyania@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I4fd52eb732fc3e6a8bccd96cad7dc090b2161042
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- 31 Dec, 2020 1 commit
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Madhukar Pappireddy authored
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- 23 Dec, 2020 11 commits
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Madhukar Pappireddy authored
* changes: ti: k3: Introduce lite device board support ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition ti: k3: Move USE_COHERENT_MEM only for the generic board ti: k3: drivers: ti_sci: Update ti_sci_msg_req_reboot to include domain ti: k3: common: sec_proxy: Fill non-message data fields with 0x0 ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg ti: k3: common: Enable A72 erratum 1319367 ti: k3: common: Enable A53 erratum 1530924 maintainers: Update maintainers for TI port
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Pali Rohár authored
Implementation is simple, just wait for the TX FIFO to be empty. Without this patch TF-A on A3720 truncate the last line: NOTICE: BL31: Built : 16:1 With this patch TF-A on A3720 print correctly also the last line: NOTICE: BL31: Built : 19:03:31, Dec 23 2020 Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I2f2ea42beab66ba132afdb400ca7898c5419db09
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Andrew F. Davis authored
Add device support for the 'lite' K3 devices. These will use modified device addresses and allow for fewer cores to save memory. Note: This family of devices are characterized by a single cluster of ARMv8 processor upto a max of 4 processors and lack of a level 3 cache. The first generation of this family is introduced with AM642. See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I8cd2c1c9a9434646d0c72fca3162dd5bc9bd692a
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Nishanth Menon authored
There are two communication scheme that have been enabled to communicate with Secure Proxy in TI. a) A full fledged prioritized communication scheme, which involves upto 5 threads from the perspective of the host software b) A much simpler "lite" version which is just a two thread scheme involving just a transmit and receive thread scheme. The (a) system is specifically useful when the SoC is massive involving multiple processor systems and where the potential for priority inversion is clearly a system usecase killer. However, this comes with the baggage of significant die area for larger number of instances of secure proxy, ring accelerator and backing memories for queued messages. Example SoCs using this scheme would be: AM654[1], J721E[2], J7200[3] etc. The (b) scheme(aka the lite scheme) is introduced on smaller SoCs where memory and area concerns are paramount. The tradeoff of priority loss is acceptable given the reduced number of processors communicating with the central system controller. This brings about a very significant area and memory usage savings while the loss of communication priority has no demonstrable impact. Example SoC using this scheme would be: AM642[4] While we can detect using JTAG ID and conceptually handle things dynamically, adding such a scheme involves a lot of unused data (cost of ATF memory footprint), pointer lookups (performance cost) and still due to follow on patches, does'nt negate the need for a different build configuration. However, (a) and (b) family of SoCs share the same scheme and addresses etc, this helps minimize our churn quite a bit Instead of introducing a complex data structure lookup scheme, lets keep things simple by first introducing the pieces necessary for an alternate communication scheme, then introduce a second platform representing the "lite" family of K3 processors. NOTE: This is only possible since ATF uses just two (secure) threads for actual communication with the central system controller. This is sufficient for the function that ATF uses. The (a) scheme and the (b) scheme also varies w.r.t the base addresses used, even though the memory window assigned for them have remained consistent. We introduce the delta as part of this change as well. This is expected to remain consistent as a standard in TI SoCs. References: [1] See AM65x Technical Reference Manual (SPRUID7, April 2018) for further details: https://www.ti.com/lit/pdf/spruid7 [2] See J721E Technical Reference Manual (SPRUIL1, May 2019) for further details: https://www.ti.com/lit/pdf/spruil1 [3] See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 [4] See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I697711ee0e6601965015ddf950fdfdec8e759bfc
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Nishanth Menon authored
commit 65f7b817 ("ti: k3: common: Use coherent memory for shared data") introduced WARMBOOT_ENABLE_DCACHE_EARLY and USE_COHERENT_MEM to handle multiple clusters across L3 cache systems. This is represented by "generic" board in k3 platform. On "lite" platforms, however, system level coherency is lacking since we don't have a global monitor or an L3 cache controller. Though, at a cluster level, ARM CPU level coherency is very much possible since the max number of clusters permitted in lite platform configuration is "1". However, we need to be able to disable USE_COHERENT_MEM for the lite configuration due to the lack of system level coherency. See docs/getting_started/build-options.rst for further information. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I4a0ec150b3f9ea12369254aef834a6cbe82d6be6
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Suman Anna authored
The ti_sci_msg_req_reboot message payload has been extended to include a domain field, and this should be zero to reset the entire SoC with System Firmwares newer than v2020.04. Add the domain field to the ti_sci_msg_req_reboot message structure for completeness. Set it up to zero to fix the reboot issues with newer firmwares. This takes care of the specific ABI that changed and has an impact on ATF function. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I4f8064b9d6555687822dc2b2b8ec97609286fa0b
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Nishanth Menon authored
Sec proxy data buffer is 60 bytes with the last of the registers indicating transmission completion. This however poses a bit of a challenge. The backing memory for sec_proxy is regular memory, and all sec proxy does is to trigger a burst of all 60 bytes of data over to the target thread backing ring accelerator. It doesn't do a memory scrub when it moves data out in the burst. When we transmit multiple messages, remnants of previous message is also transmitted which results in some random data being set in TISCI fields of messages that have been expanded forward. The entire concept of backward compatibility hinges on the fact that the unused message fields remain 0x0 allowing for 0x0 value to be specially considered when backward compatibility of message extension is done. So, instead of just writing the completion register, we continue to fill the message buffer up with 0x0 (note: for partial message involving completion, we already do this). This allows us to scale and introduce ABI changes back into TF-A only as needed. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: Ie22cb2a319f4aa80aef23ffc7e059207e5d4c640
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Nishanth Menon authored
ARM's generic timer[1] picks up it's graycode from GTC. However, the frequency of the GTC is supposed to be programmed in CNTFID0[2] register. In K3, architecture, GTC provides a central time to many parts of the SoC including graycode to the generic timer in the ARMv8 subsystem. However, due to the central nature and the need to enable the counter early in the boot process, the R5 based bootloader enables GTC and programs it's frequency based on central needs of the system. This may not be a constant 200MHz based on the system. The bootloader is supposed to program the FID0 register with the correct frequency it has sourced for GTC from the central system controller, and TF-A is supposed to use that as the frequency for it's local timer. A mismatch in programmed frequency and what we program for generic timer will, as we can imagine, all kind of weird mayhem. So, check the CNTFID0 register, if it is 0, warn and use the default frequency to continue the boot process. While at it, we can also check CNTCR register to provide some basic diagnostics to make sure that we don't have OS folks scratch their heads. Even though this is used during cpu online operations, the cost of this additional check is minimal enough for us not to use #ifdeffery with DEBUG flags. [1] https://developer.arm.com/documentation/100095/0002/generic-timer/generic-timer-register-summary/aarch64-generic-timer-register-summary [2] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntfid0 [3] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntcr Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: Ib03e06788580f3540dcb1a11677d0d6d398b2c9f
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Nishanth Menon authored
The CatB erratum ARM_ERRATA_A72_1319367 applies to all TI A72 platforms as well. See the following for further information: https://developer.arm.com/documentation/epm012079/11/ Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I80c6262b9cdadcb12f6dfd5a21272989ba257719
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Nishanth Menon authored
The CatB erratum ARM_ERRATA_A53_1530924 applies to all TI A53 platforms as well. See the following for further information: https://developer.arm.com/documentation/epm048406/2100 Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: Ic095424ce510139e060b38cfb84509d2cc573cad
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Nishanth Menon authored
Andrew is no longer with TI unfortunately, so stepping up to provide maintainer for supported TI platforms. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: Ia1be294631421913bcbc3d346947195cb442d437
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- 22 Dec, 2020 8 commits
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Madhukar Pappireddy authored
* changes: zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls zynqmp: pm: Reimplement pinctrl set/get function EEMI API zynqmp: pm: Implement pinctrl request/release EEMI API zynqmp: pm: Update return type in query functions
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Madhukar Pappireddy authored
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Madhukar Pappireddy authored
* changes: mediatek: mt8192: add rtc power off sequence mediatek: mt8192: Fix non-MISRA compliant code mediatek: mt8192: Fix non-MISRA compliant code mediatek: mt8192: Add MPU support
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André Przywara authored
* changes: allwinner: Add SPC security setup for H6 allwinner: Add R_PRCM security setup for H6
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André Przywara authored
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André Przywara authored
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André Przywara authored
* changes: allwinner: Use RSB for the PMIC connection on H6 allwinner: Return the PMIC to I2C mode after use allwinner: Always use a 3MHz RSB bus clock
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Graeme Gregory authored
In psci_setup.c psci_init_pwr_domain_node() takes an unsigned char as node_idx which limits it to initialising only the first 256 CPUs. As the calling function does not check for a limit of 256 I think this is a bug so change the unsigned char to uint16_t and change the cast from the calling site in populate_power_domain_tree(). Also update the non_cpu_pwr_domain_node structure lock_index to uint16_t and update the function signature for psci_lock_init() appropriately. Finally add a define PSCI_MAX_CPUS_INDEX to psci_private.h and add a CASSERT to psci_setup.c to make sure PLATFORM_CORE_COUNT cannot exceed the index value. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I9e26842277db7483fd698b46bbac62aa86e71b45
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- 21 Dec, 2020 1 commit
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Madhukar Pappireddy authored
* changes: fdts: tc0: Add reserved-memory node for OP-TEE plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2 docs: arm: Add OPTEE_SP_FW_CONFIG plat: tc0: enable opteed support plat: arm: Increase SP max size
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- 18 Dec, 2020 2 commits
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bipin.ravi authored
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johpow01 authored
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions of the A76 processor core. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present in revisions r0p0 - r4p1 but this workaround only applies to revisions r3p0 - r4p1, there is no workaround for older versions. SDEN can be found here: https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327
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- 16 Dec, 2020 6 commits
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Madhukar Pappireddy authored
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Yuchen Huang authored
add mt6359p rtc power off sequence and enable k_eosc mode Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.com> Change-Id: I65450c63c44ccb5082541dbbe28b8aa0a95ecc56
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Yidi Lin authored
CID 364146: Control flow issues (DEADCODE) Since the value of PSTATE_PWR_LVL_MASK and the value the of PLAT_MAX_PWR_LVL are equal on mt8192, the following equation never hold. if (aff_lvl > PLAT_MAX_PWR_LVL) { return PSCI_E_INVALID_PARAMS; } Remove the deadcode to comply with MISRA standard. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I71d0aa826eded8c3b5af961e733167ae40699398
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Yidi Lin authored
CID 364144: Integer handling issues (NO_EFFECT) The unsigned value is always greater-than-or-equal-to-zero. Remove such check. Change-Id: Ia395eb32f55a7098d2581ce7f548b7e1112beaa0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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Xi Chen authored
1 Add Domain1(PCIe device) protect address: 0x80000000~0x83FF0000. 2 Add Domain2(SSPM/SPM/DPM/MCUPM) protect address: 0x40000000~0x1FFFF0000. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I4aaed37150076ae5943484c4adadac999a3d1762
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Vijayenthiran Subramaniam authored
RD-N2 platform has been updated to use six GIC ITS blocks. This results in change in base address of the GIC Redistributor to accomodate two new GIC ITS blocks. Update the base address of GICR to reflect the same. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I740a547328fb9a9f25d7a09c08e61bdbc8bf781c
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- 15 Dec, 2020 5 commits
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Mark Dykes authored
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Mirela Simonovic authored
Functions are reimplemented to issue system-level pinctrl EEMI calls to the PMU-FW rather than using MMIO read/write. Macros and functions that appear to be unused after the change is made are removed. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I51f2285a79f202cb2ca9f031044002e16dd1e92f
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Mirela Simonovic authored
Functions are reimplemented to issue system-level pinctrl EEMI calls to the PMU-FW rather than using MMIO read/write. Macros and functions that appear to be unused after the change is made are removed. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I21b8fda855aa69090b85d6aaf411e19560201cb5
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Mirela Simonovic authored
The calls are just passed through to the PMU-FW. Before issuing other pinctrl functions the pin should be successfully requested. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: Ibce280edebedf779b3962009c274d0b3d928e0e4
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Rajan Vaja authored
In pm_query_data() function return type is stored in response so there is no use of return type. Update return type of function pm_query_data() from enum pm_ret_status to void. Similarly update return type of pm_api_clock_get_name() and pm_api_pinctrl_get_function_name() functions. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: Id811926f0b4ebcc472480bb94f3b88109eb036cd
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- 14 Dec, 2020 5 commits
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Arunachalam Ganapathy authored
Add reserved-memory region for OP-TEE and mark as no-map. This memory region is used by OP-TEE as non-secure shared RAM. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I5a22999a8c5550024d0f47e848d35924017df245
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Arunachalam Ganapathy authored
This patch adds support to enable OP-TEE as S-EL1 SP with SPMC at S-EL2 - create SPMC manifest file with OP-TEE as SP - add support for ARM_SPMC_MANIFEST_DTS build option - add optee entry with ffa as method in tc0.dts Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Ia9b5c22c6f605d3886914bbac8ac45e8365671cb
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Arunachalam Ganapathy authored
This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Ie45f075cf04182701007f87aa0c8912cd567157a
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Arunachalam Ganapathy authored
Enable SPD=opteed support for tc0 platform. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Ieb038d645c68fbe6b5a211c7279569e21b476fc3
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Arunachalam Ganapathy authored
Increase SP max size for latest OP-TEE build with debug and stats enabled. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I4593884e0deb39ada10009f6876d815136f8ee65
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