1. 23 Mar, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra186: save/restore BL31 context to/from TZDRAM · 68c7de6f
      Varun Wadekar authored
      
      
      This patch adds support to save the BL31 state to the TZDRAM
      before entering system suspend. The TZRAM loses state during
      system suspend and so we need to copy the entire BL31 code to
      TZDRAM before entering the state.
      
      In order to restore the state on exiting system suspend, a new
      CPU reset handler is implemented which gets copied to TZDRAM
      during boot. TO keep things simple we use this same reset handler
      for booting secondary CPUs too.
      
      Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      68c7de6f
  2. 28 Feb, 2017 5 commits
    • Varun Wadekar's avatar
      Tegra: get BL31 arguments from previous bootloader · 8ab06d2f
      Varun Wadekar authored
      
      
      This patch implements handlers which platforms can override to
      get the BL31 arguments passed by the previous bootloader.
      
      Change-Id: I6b9628a984644ce1b5de5aa6d7cd890e57241d89
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8ab06d2f
    • Varun Wadekar's avatar
      Tegra: GIC: differentiate between FIQs targeted towards EL3/S-EL1 · 45eab456
      Varun Wadekar authored
      
      
      This patch modifies the secure IRQ registration process to allow platforms
      to specify the target CPUs as well as the owner of the IRQ. IRQs "owned"
      by the EL3 would return INTR_TYPE_EL3 whereas those owned by the Trusted
      OS would return INTR_TYPE_S_EL1 as a result.
      
      Change-Id: I528f7c8220d0ae0c0f354e78d69e188abb666ef6
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      45eab456
    • Varun Wadekar's avatar
      Tegra: implement FIQ interrupt handler · 78e2bd10
      Varun Wadekar authored
      
      
      This patch adds a handler for FIQ interrupts triggered when
      the CPU is in the NS world. The handler stores the NS world's
      context along with ELR_EL3/SPSR_EL3.
      
      The NS world driver issues an SMC initially to register it's
      handler. The monitor firmware stores this handler address and
      jumps to it when the FIQ interrupt fires. Upon entry into the
      NS world the driver then issues another SMC to get the CPU
      context when the FIQ fired. This allows the NS world driver to
      determine the CPU state and call stack when the interrupt
      fired. Generally, systems register watchdog interrupts as FIQs
      which are then used to get the CPU state during hangs/crashes.
      
      Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      78e2bd10
    • Varun Wadekar's avatar
      Tegra: GIC: enable FIQ interrupt handling · d3360301
      Varun Wadekar authored
      
      
      Tegra chips support multiple FIQ interrupt sources. These interrupts
      are enabled in the GICD/GICC interfaces by the tegra_gic driver. A
      new FIQ handler would be added in a subsequent change which can be
      registered by the platform code.
      
      This patch adds the GIC programming as part of the tegra_gic_setup()
      which now takes an array of all the FIQ interrupts to be enabled for
      the platform. The Tegra132 and Tegra210 platforms right now do not
      register for any FIQ interrupts themselves, but will definitely use
      this support in the future.
      
      Change-Id: I0ea164be901cd6681167028fea0567399f18d4b8
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d3360301
    • Varun Wadekar's avatar
      Tegra: handler for per-soc early setup · 5ea0b028
      Varun Wadekar authored
      
      
      This patch adds a weak handler for early platform setup which
      can be overriden by the soc-specific handlers to perform any
      early setup tasks.
      
      Change-Id: I1a7a98d59b2332a3030c6dca5a9b7be977177326
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5ea0b028
  3. 22 Feb, 2017 2 commits
    • Varun Wadekar's avatar
      Tegra: init normal/crash console for platforms · e1084216
      Varun Wadekar authored
      
      
      The BL2 fills in the UART controller ID to be used as the normal as
      well as the crash console on Tegra platforms. The controller ID to
      UART controller base address mapping is handled by each Tegra SoC
      the base addresses might change across Tegra chips.
      
      This patch adds the handler to parse the platform params to get the
      UART ID for the per-soc handlers.
      
      Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e1084216
    • Varun Wadekar's avatar
      Tegra: add tzdram_base to plat_params_from_bl2 struct · e0d4158c
      Varun Wadekar authored
      
      
      This patch adds another member, tzdram_base, to the plat_params_from_bl2 struct
      in order to store the TZDRAM carveout base address used to load the Trusted OS.
      The monitor programs the memory controller with the TZDRAM base and size in order
      to deny any accesses from the NS world.
      
      Change-Id: If39b8674d548175d7ccb6525c18d196ae8a8506c
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e0d4158c
  4. 20 May, 2016 1 commit
  5. 21 Apr, 2016 1 commit
    • Yatharth Kochar's avatar
      Move `plat_get_syscnt_freq()` to arm_common.c · c073fda1
      Yatharth Kochar authored
      This patch moves the definition for `plat_get_syscnt_freq()`
      from arm_bl31_setup.c to arm_common.c. This could be useful
      in case a delay timer needs to be installed based on the
      generic timer in other BLs.
      This patch also modifies the return type for this function
      from `uint64_t` to `unsigned long long` within ARM and other
      platform files.
      
      Change-Id: Iccdfa811948e660d4fdcaae60ad1d700e4eda80d
      c073fda1
  6. 09 Dec, 2015 1 commit
    • Yatharth Kochar's avatar
      Include psci.h from tegra platform header · ca8b7d51
      Yatharth Kochar authored
      The `plat/nvidia/tegra/include/tegra_private.h` file uses resources
      from psci.h (for example, psci_power_state_t) but does not explicitly
      include psci.h. This does not currently cause a problem since psci.h
      is indirectly included via other headers. However, this may not be
      the case in future.
      
      This patch explicitly includes psci.h from tegra_private.h
      
      Change-Id: Ia991147898dbd117c1d3496a95850995a5554c05
      ca8b7d51
  7. 04 Dec, 2015 1 commit
  8. 31 Jul, 2015 1 commit
  9. 24 Jul, 2015 1 commit
  10. 17 Jul, 2015 1 commit
  11. 12 Jun, 2015 1 commit
    • Varun Wadekar's avatar
      Reserve a Video Memory aperture in DRAM memory · 9a964510
      Varun Wadekar authored
      
      
      This patch adds support to reserve a memory carveout region in the
      DRAM on Tegra SoCs. The memory controller provides specific registers
      to specify the aperture's base and size. This aperture can also be
      changed dynamically in order to re-size the memory available for
      DRM video playback. In case of the new aperture not overlapping
      the previous one, the previous aperture has to be cleared before
      setting up the new one. This means we do not "leak" any video data
      to the NS world.
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      9a964510
  12. 29 May, 2015 1 commit
    • Varun Wadekar's avatar
      Support for NVIDIA's Tegra T210 SoCs · 08438e24
      Varun Wadekar authored
      
      
      T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
      ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
      at a given point in time.
      
      This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
      also adds support to boot secondary CPUs, enter/exit core power states for
      all CPUs in the slow/fast clusters. The support to switch between clusters
      is still not available in this patch and would be available later.
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      08438e24
  13. 28 Apr, 2015 1 commit
    • Dan Handley's avatar
      Add common ARM and CSS platform code · b4315306
      Dan Handley authored
      This major change pulls out the common functionality from the
      FVP and Juno platform ports into the following categories:
      
      *   (include/)plat/common. Common platform porting functionality that
      typically may be used by all platforms.
      
      *   (include/)plat/arm/common. Common platform porting functionality
      that may be used by all ARM standard platforms. This includes all
      ARM development platforms like FVP and Juno but may also include
      non-ARM-owned platforms.
      
      *   (include/)plat/arm/board/common. Common platform porting
      functionality for ARM development platforms at the board
      (off SoC) level.
      
      *   (include/)plat/arm/css/common. Common platform porting
      functionality at the ARM Compute SubSystem (CSS) level. Juno
      is an example of a CSS-based platform.
      
      *   (include/)plat/arm/soc/common. Common platform porting
      functionality at the ARM SoC level, which is not already defined
      at the ARM CSS level.
      
      No guarantees are made about the backward compatibility of
      functionality provided in (include/)plat/arm.
      
      Also remove any unnecessary variation between the ARM development
      platform ports, including:
      
      *   Unify the way BL2 passes `bl31_params_t` to BL3-1. Use the
      Juno implementation, which copies the information from BL2 memory
      instead of expecting it to persist in shared memory.
      
      *   Unify the TZC configuration. There is no need to add a region
      for SCP in Juno; it's enough to simply not allow any access to
      this reserved region. Also set region 0 to provide no access by
      default instead of assuming this is the case.
      
      *   Unify the number of memory map regions required for ARM
      development platforms, although the actual ranges mapped for each
      platform may be different. For the FVP port, this reduces the
      mapped peripheral address space.
      
      These latter changes will only be observed when the platform ports
      are migrated to use the new common platform code in subsequent
      patches.
      
      Change-Id: Id9c269dd3dc6e74533d0e5116fdd826d53946dc8
      b4315306
  14. 28 Jan, 2015 1 commit
    • Juan Castillo's avatar
      TBB: add tool to generate certificates · 6f971622
      Juan Castillo authored
      This patch adds a tool that generates all the necessary elements
      to establish the chain of trust (CoT) between the images.
      
      The tool reads the binary images and signing keys and outputs the
      corresponding certificates that will be used by the target at run
      time to verify the authenticity of the images.
      
      Note: the platform port must provide the file platform_oid.h. This
      file will define the OIDs of the x509 extensions that will be added
      to the certificates in order to establish the CoT.
      
      Change-Id: I2734d6808b964a2107ab3a4805110698066a04be
      6f971622
  15. 17 Jan, 2014 1 commit
  16. 20 Dec, 2013 2 commits
    • Harry Liebel's avatar
      Add strchr() and putchar() to local C library · 1bc9e1f6
      Harry Liebel authored
      Change-Id: I3659e119a242f8ef828e32bfdf5d0b4b7ac4f716
      1bc9e1f6
    • Harry Liebel's avatar
      Create local C library implementation (2/2) · 0f702c6e
      Harry Liebel authored
      - This change is split into two separate patches in order to
        simplify the history as interpreted by 'git'. The split is
        between the move/rename and addition of new files.
      - Remove dependency on toolchain C library headers and functions in
        order to ensure behavioural compatibility between toolchains.
      - Use FreeBSD as reference for C library implementation.
      - Do not let GCC use default library include paths.
      - Remove unused definitions in modified headers and implementations.
      - Move C library files to 'lib/stdlib' and 'include/stdlib'.
      - Break std.c functions out into separate files.
      
      Change-Id: I3e3d8d992052264d2a02489034ae4c03bf0f5512
      0f702c6e
  17. 05 Dec, 2013 1 commit
    • Dan Handley's avatar
      Enable third party contributions · ab2d31ed
      Dan Handley authored
      - Add instructions for contributing to ARM Trusted Firmware.
      
      - Update copyright text in all files to acknowledge contributors.
      
      Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5
      ab2d31ed
  18. 25 Oct, 2013 1 commit