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  1. 12 Mar, 2020 1 commit
    • Chris Kay's avatar
      juno/sgm: Maximize space allocated to SCP_BL2 · ddc93cba
      Chris Kay authored 
      

To accommodate the increasing size of the SCP_BL2 binary, the base
address of the memory region allocated to SCP_BL2 has been moved
downwards from its current (mostly) arbitrary address to the beginning
of the non-shared trusted SRAM.

Change-Id: I086a3765bf3ea88f45525223d765dc0dbad6b434
Signed-off-by: default avatarChris Kay <chris.kay@arm.com>
      ddc93cba
  3. 10 Mar, 2020 1 commit
  5. 03 Mar, 2020 2 commits
  7. 25 Feb, 2020 1 commit
    • Alexei Fedorov's avatar
      FVP: Fix incorrect GIC mapping · b3c431f3
      Alexei Fedorov authored 
      

This patch fixes incorrect setting for DEVICE1_SIZE
for FVP platforms with more than 8 PEs.
The current value of 0x200000 supports only 8 PEs
and causes exception for FVP platforms with the greater
number of PEs, e.g. FVP_Base_Cortex_A65AEx8 with 16 PEs
in one cluster.

Change-Id: Ie6391509fe6eeafb8ba779303636cd762e7d21b2
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      b3c431f3
  9. 24 Feb, 2020 5 commits
    • Petre-Ionut Tudor's avatar
      Read-only xlat tables for BL31 memory · 60e8f3cf
      Petre-Ionut Tudor authored 
      

This patch introduces a build flag which allows the xlat tables
to be mapped in a read-only region within BL31 memory. It makes it
much harder for someone who has acquired the ability to write to
arbitrary secure memory addresses to gain control of the
translation tables.

The memory attributes of the descriptors describing the tables
themselves are changed to read-only secure data. This change
happens at the end of BL31 runtime setup. Until this point, the
tables have read-write permissions. This gives a window of
opportunity for changes to be made to the tables with the MMU on
(e.g. reclaiming init code). No changes can be made to the tables
with the MMU turned on from this point onwards. This change is also
enabled for sp_min and tspd.

To make all this possible, the base table was moved to .rodata. The
penalty we pay is that now .rodata must be aligned to the size of
the base table (512B alignment). Still, this is better than putting
the base table with the higher level tables in the xlat_table
section, as that would cost us a full 4KB page.

Changing the tables from read-write to read-only cannot be done with
the MMU on, as the break-before-make sequence would invalidate the
descriptor which resolves the level 3 page table where that very
descriptor is located. This would make the translation required for
writing the changes impossible, generating an MMU fault.

The caches are also flushed.
Signed-off-by: default avatarPetre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: Ibe5de307e6dc94c67d6186139ac3973516430466
      60e8f3cf
    • Sandrine Bailleux's avatar
      plat/arm: Retrieve the right ROTPK when using the dualroot CoT · d25625ca
      Sandrine Bailleux authored 
      

The dualroot chain of trust involves 2 root-of-trust public keys:
- The classic ROTPK.
- The platform ROTPK (a.k.a. PROTPK).

Use the cookie argument as a key ID for plat_get_rotpk_info() to return the
appropriate one. This only applies if we are using the dualroot CoT ; if using
the TBBR one, the behaviour is unchanged.

Change-Id: I400707a87ec01afd5922b68db31d652d787f79bd
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      d25625ca
    • Sandrine Bailleux's avatar
      plat/arm: Pass cookie argument down to arm_get_rotpk_info() · 88005701
      Sandrine Bailleux authored 
      

The cookie will be leveraged in the next commit.

Change-Id: Ie8bad275d856d84c27466461cf815529dd860446
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      88005701
    • Sandrine Bailleux's avatar
      plat/arm: Add support for dualroot CoT · 1035a706
      Sandrine Bailleux authored 
      

- Use the development PROTPK if using the dualroot CoT.

  Note that unlike the ROTPK, the PROTPK key hash file is not generated
  from the key file, instead it has to be provided. This might be
  enhanced in the future.

- Define a CoT build flag for the platform code to provide different
  implementations where needed.

Change-Id: Iaaf25183b94e77a99a5d8d875831d90c102a97ea
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      1035a706
    • Sandrine Bailleux's avatar
      plat/arm: Provide some PROTK files for development · 32e26c06
      Sandrine Bailleux authored 
      

When using the new dualroot chain of trust, a new root of trust key is
needed to authenticate the images belonging to the platform owner.
Provide a development one to deploy this on Arm platforms.

Change-Id: I481145e09aa564822d474cb47d38ec211dd24efd
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      32e26c06
  11. 19 Feb, 2020 4 commits
  13. 18 Feb, 2020 4 commits
  15. 17 Feb, 2020 3 commits
    • Vishnu Banavath's avatar
      corstone700: set UART clocks to 32MHz · 6aa138de
      Vishnu Banavath authored 
      

Adding support for 32MHz UART clock and selecting it as the
default UART clock

Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c
Signed-off-by: default avatarVishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: default avatarAbdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
      6aa138de
    • Avinash Mehta's avatar
      corstone700: clean-up as per coding style guide · 93cf1f64
      Avinash Mehta authored 
      

Running checkpatch.pl on the codebase and making required changes

Change-Id: I7d3f8764cef632ab2a6d3c355c68f590440b85b8
Signed-off-by: default avatarAvinash Mehta <avinash.mehta@arm.com>
Signed-off-by: default avatarAbdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
      93cf1f64
    • Khandelwal's avatar
      Corstone700: add support for mhuv2 in arm TF-A · c6fe43b7
      Khandelwal authored 
      

Note: This patch implements in-band messaging protocol only.
ARM has launched a next version of MHU i.e. MHUv2 with its latest
subsystems. The main change is that the MHUv2 is now a distributed IP
with different peripheral views (registers) for the sender and receiver.

Another main difference is that MHUv1 duplex channels are now split into
simplex/half duplex in MHUv2. MHUv2 has a configurable number of
communication channels. There is a capability register (MSG_NO_CAP) to
find out how many channels are available in a system.

The register offsets have also changed for STAT, SET & CLEAR registers
from 0x0, 0x8 & 0x10 in MHUv1 to 0x0, 0xC & 0x8 in MHUv2 respectively.

0x0    0x4  0x8  0xC             0x1F
------------------------....-----
| STAT |    |    | SET |    |   |
------------------------....-----
      Transmit Channel

0x0    0x4  0x8   0xC            0x1F
------------------------....-----
| STAT |    | CLR |    |    |   |
------------------------....-----
        Receive Channel

The MHU controller can request the receiver to wake-up and once the
request is removed, the receiver may go back to sleep, but the MHU
itself does not actively put a receiver to sleep.

So, in order to wake-up the receiver when the sender wants to send data,
the sender has to set ACCESS_REQUEST register first in order to wake-up
receiver, state of which can be detected using ACCESS_READY register.
ACCESS_REQUEST has an offset of 0xF88 & ACCESS_READY has an offset
of 0xF8C and are accessible only on any sender channel.

This patch adds necessary changes in a new file required to support the
latest MHUv2 controller. This patch also needs an update in DT binding
for ARM MHUv2 as we need a second register base (tx base) which would
be used as the send channel base.

Change-Id: I1455e08b3d88671a191c558790c503eabe07a8e6
Signed-off-by: default avatarTushar Khandelwal <tushar.khandelwal@arm.com>
      c6fe43b7
  17. 13 Feb, 2020 1 commit
  19. 12 Feb, 2020 1 commit
  21. 11 Feb, 2020 1 commit
  23. 10 Feb, 2020 2 commits
  25. 07 Feb, 2020 14 commits