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The macro has n > 32.
It has to be n > 31 since GPIO 0-31 are on Register 0 and 32-63 on Register 1.
Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>

juno:Fix CSS_USE_SCMI_SDS_DRIVER=0 configuration

A previous commit 89f2e589

 ("plat/arm: remove weak implemention of
'plat_arm_psci_override_pm_ops' function") introduced a problem with the
CSS_USE_SCMI_SDS_DRIVER configuration. In juno_pm.c the
css_scmi_override_pm_ops function was used regardless of whether the
flag was set. This patch ifdefs the function to restore the original
behaviour.

Change-Id: I508025ba70cf3a9250cc6270c1df209179c37ae7
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>

Arm/master/update rcar 2.0.0

Update the reported Renesas version to 2.0.0, since the DDR/QoS/PFC
table versions match the ones from that release.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Replace the ad-hoc implementation of delay in PWRC driver
with common R-Car delay code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Rewrite the delay code from assembler to C.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Add code to determine the platform timer frequency and configure
the generic timer accordingly early in BL2.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Use the SCIF SCFSR:TEND bit to check that all data were transmitted by
the SCIF and that there are no more valid data to transmit in the FIFO.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Synchronize the QoS tables with Renesas ATF release 2.0.0 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Synchronize the pin control tables with Renesas ATF release 2.0.0 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Synchronize the R-Car DDR-B driver, used on R-Car H3/M3W/M3N,
with Renesas ATF release 2.0.0 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Run Linux kernel checkpatch on the DDR-A init code to clean it up:
$ checkpatch.pl --fix --fix-inplace -f drivers/staging/renesas/rcar/ddr/ddr_a/*
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Synchronize the R-Car DDR-A driver, used on R-Car E3,
with Renesas ATF release 2.0.0 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Move the rcar_cpld_reset_cpu() function into header file and zap the externs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

The code runs in EL3, use EL3 accessors to manipulate the interrupt bit.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

The code runs in EL3, use EL3 accessors to manipulate the cache bits.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Since the interrupts are handled in EL3, dump the EL3 error registers
in case an error happens.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

The reset address is programmable on the R-Car Gen3, enable it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Disable the IPMMU PV0 cache on E3 rev. 1.x .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Add support for R-Car E3 silicon rev. 1.1
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Add missing TARGET_NAME for the case where RCAR_LSI is set to AUTO,
which is platform auto-detection.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Call the function only from architecture setup and at the end of
suspend cycle instead of calling it all over the place.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to
correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the
hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable
BL2 area.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Staticize the platform memory map tables as they are only used within
the platform_common.c file.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Replace foo_t with struct foo.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

The CPU has cache line size of 64 Bytes, fix the cache line size.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Apply 3872fc2d

 ("Do not enable SVE on pre-v8.2 platforms") to
R-Car Gen3 too.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Add missing dependency on the bl2.elf and bl31.elf into the rcar_srecord
target, which uses those ELF files to generate the SRECs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Rename the H3 label to avoid confusing clang, which generates an error
if the label is just H3. Rename it to RCARH3.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

This function is unused and triggers clang error, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

plat/arm: Restrict PIE support to FVP

Fix a variable expansion in Arm platform makefiles

plat/arm/n1sdp: define the uart constants for N1SDP

stm32mp1: do not include platform header files directly in drivers

maintainers: Fix path of Marvell documentation

plat: xilinx: Clock and PLL EEMI API Support

This patch removes the dependency of the N1SDP on soc
css defines in order to let the N1SDP platform port
define the uart related constants.

Change-Id: If13796f278586a01512ee99615502b30e478189e
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>

The top level makefile defines the PLAT variable, not PLATFORM.
This mistake was causing an empty variable expansion and showing an
incomplete error message.

Change-Id: I5da1275c73c61a7c1823643a76300f255841719d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

The patch SHA 55cf015c

 enabled PIE support when RESET_TO_BL31=1 for
all ARM platforms. But it seems n1sdp platform doesn't work with PIE
support yet. Hence restrict the ENABLE_PIE=1 to fvp platform.

Change-Id: If44e42528e4b0b57c69084503f346576fe0748bd
Signed-off-by: Soby Mathew <soby.mathew@arm.com>