Skip to content

GitLab

Switch branch/tag
  1. 07 Jan, 2020 5 commits
    • Mirela Simonovic's avatar
      zynqmp: pm: Fix clock models and IDs of GEM-related clocks · 06ad9803
      Mirela Simonovic authored 
      

GEM-related clock models were incorrect and are fixed as follows
(documented below for GEM0, but the same holds for any GEM ID):

- CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and
 the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this
 clock is newly introduced in this patch.

- CLK_GEM0_REF models the clock mux that selects the reference clock
 for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This
 mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL.
 Note that the routing of external clock to the mux is not modelled
 and is assumed to be configured by the FSBL if required, and not
 changeable at runtime. The ID of this clock is introduced in this patch.

- CLK_GEM0_TX models clock with only a gate that is controlled via
 bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is
 CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID
 value of CLK_GEM0_REF. This is done in order to fix the clock models
 and incorrect binding without requiring to change device-tree (binding
 of clock IDs to GEM interface).

- CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT
 bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced
 from external RGMII PHY (via MIO or EMIO). We do not model the whole
 clock path to the Rx gate, since this is configured by the FSBL and
 never changed at runtime (and there is no mechanism to change the
 path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the
 previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX
 were swapped in device tree, so by fixing the IDs this way there is no
 need for device tree fix.

Rates of the external RX/TX clocks can be specified in device tree if
needed. Right now, that's not necessary because Tx clock is sourced
from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas
the Rx clock is sourced from external reference and the driver never
attempts to get/get clock rate (only to enable it). If this changes in
future, ATF clock model doesn't need to be changed. Instead, the clock
rates for gem0_tx_ext and gem0_rx_ext have to be specified in device
tree.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <will.wong@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Change-Id: I6497d4309e92205c527bd81b3aa932f4474f5b79
      06ad9803
    • Mounika Grace Akula's avatar
      zynqmp: pm: Rename FPD WDT clock ID · fa8ae3c8
      Mounika Grace Akula authored 
      

This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT.
Signed-off-by: default avatarMounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Change-Id: I4d00a59b1dc54920115a2da55e8a06347fe2231c
      fa8ae3c8
    • Edgar E. Iglesias's avatar
      plat: xilinx: zynqmp: Correct syscnt freq for QEMU · 65501a7c
      Edgar E. Iglesias authored 
      

Correct the syscnt frequency for ZynqMP QEMU to 65Mhz.
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Change-Id: Ie0137feb9b7e24ed4e5d6cbf81c58ac77bb69214
      65501a7c
    • Venkatesh Yadav Abbarapu's avatar
      arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR · c613a660
      Venkatesh Yadav Abbarapu authored 
      

Add support for zu48dr and zu49dr to the list of zynqmp devices. The
zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b
and 0x7e.
Signed-off-by: default avatarVenkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Change-Id: I2978f16bb663853951ef8059bf0327f909447f34
      c613a660
    • Siva Durga Prasad Paladugu's avatar
      arm64: zynqmp: Add id for new RFSoC device ZU39DR · 345a85ae
      Siva Durga Prasad Paladugu authored 
      

This patch adds new RFSoC device ZU39DR to zynqmp
devices list
Signed-off-by: default avatarSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Change-Id: I35735da9e7d7facbde44323c49eac1b714e4909d
      345a85ae
  3. 03 Jan, 2020 1 commit
    • Vishnu Banavath's avatar
      drivers: add a driver for snoop control unit · c20c0525
      Vishnu Banavath authored 
      

The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.

The SCU functions are to:
- maintain data cache coherency between the Cortex-A5/Cortex-A9
  processors
- initiate L2 AXI memory accesses
- arbitrate between Cortex-A5/Cortex-A9 processors requesting
  L2 accesses
- manage ACP accesses.

Snoop Control Unit will enable to snoop on other CPUs caches.
This is very important when it comes to synchronizing data between
CPUs. As an example, there is a high chance that data might be
cache'd and other CPUs can't see the change. In such cases,
if snoop control unit is enabled, data is synchoronized immediately
between CPUs and the changes are visible to other CPUs.

This driver provides functionality to enable SCU as well as enabling
user to know the following
- number of CPUs present
- is a particular CPU operating in SMP mode or AMP mode
- data cache size of a particular CPU
- does SCU has ACP port
- is L2CPRESENT

Change-Id: I0d977970154fa60df57caf449200d471f02312a0
Signed-off-by: default avatarVishnu Banavath <vishnu.banavath@arm.com>
      c20c0525
  5. 29 Dec, 2019 1 commit
  7. 26 Dec, 2019 2 commits
  9. 20 Dec, 2019 5 commits
    • Paul Beesley's avatar
      spm-mm: Remove mm_svc.h header · 962c44e7
      Paul Beesley authored 
      

The contents of this header have been merged into the spm_mm_svc.h
header file.

Change-Id: I01530b2e4ec1b4c091ce339758025e2216e740a4
Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      962c44e7
    • Paul Beesley's avatar
      spm-mm: Refactor spm_svc.h and its contents · 0bf9f567
      Paul Beesley authored 
      

Change-Id: I91c192924433226b54d33e57d56d146c1c6df81b
Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      0bf9f567
    • Paul Beesley's avatar
      spm-mm: Refactor secure_partition.h and its contents · aeaa225c
      Paul Beesley authored 
      

Before adding any new SPM-related components we should first do
some cleanup around the existing SPM-MM implementation. The aim
is to make sure that any SPM-MM components have names that clearly
indicate that they are MM-related. Otherwise, when adding new SPM
code, it could quickly become confusing as it would be unclear to
which component the code belongs.

The secure_partition.h header is a clear example of this, as the
name is generic so it could easily apply to any SPM-related code,
when it is in fact SPM-MM specific.

This patch renames the file and the two structures defined within
it, and then modifies any references in files that use the header.

Change-Id: I44bd95fab774c358178b3e81262a16da500fda26
Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      aeaa225c
    • Paul Beesley's avatar
      spm: Remove SPM Alpha 1 prototype and support files · 538b0020
      Paul Beesley authored 
      

The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component that, in turn, enables partition managers
at S-EL2 / S-EL1.

This patch removes:

- The core service files (std_svc/spm)
- The Resource Descriptor headers (include/services)
- SPRT protocol support and service definitions
- SPCI protocol support and service definitions

Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426
Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
Signed-off-by: default avatarArtsem Artsemenka <artsem.artsemenka@arm.com>
      538b0020
    • Paul Beesley's avatar
      Remove dependency between SPM_MM and ENABLE_SPM build flags · 3f3c341a
      Paul Beesley authored 
      

There are two different implementations of Secure Partition
management in TF-A. One is based on the "Management Mode" (MM)
design, the other is based on the Secure Partition Client Interface
(SPCI) specification. Currently there is a dependency between their
build flags that shouldn't exist, making further development
harder than it should be. This patch removes that
dependency, making the two flags function independently.

Before: ENABLE_SPM=1 is required for using either implementation.
        By default, the SPCI-based implementation is enabled and
        this is overridden if SPM_MM=1.

After: ENABLE_SPM=1 enables the SPCI-based implementation.
       SPM_MM=1 enables the MM-based implementation.
       The two build flags are mutually exclusive.

Note that the name of the ENABLE_SPM flag remains a bit
ambiguous - this will be improved in a subsequent patch. For this
patch the intention was to leave the name as-is so that it is
easier to track the changes that were made.

Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a
Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      3f3c341a
  11. 19 Dec, 2019 1 commit
  13. 18 Dec, 2019 2 commits
  15. 17 Dec, 2019 20 commits
  17. 14 Dec, 2019 3 commits
    • Samuel Holland's avatar
      allwinner: h6: power: Switch to using the AXP driver · fb23b104
      Samuel Holland authored 
      

Chip ID checking and poweroff work just like they did before.
Regulators are now enabled just like on A64/H5.

This changes the signatures of the low-level register read/write
functions to match the interface expected by the common driver.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Change-Id: I14d63d171a094fa1375904928270fa3e21761646
      fb23b104
    • Samuel Holland's avatar
      allwinner: Convert AXP803 regulator setup code into a driver · 0bc752c9
      Samuel Holland authored 
      

Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely
independent. However, some H6 boards also need early regulator setup.

Most of the register interface and all of the device tree traversal code
can be reused between the AXP803 and AXP805. The main difference is the
hardware bus interface, so that part is left to the platforms. The
remainder is moved into a driver.

I factored out the bits that were obviously specific to the AXP803;
additional changes for compatibility with other PMICs can be made as
needed.

The only functional change is that rsb_init() now checks the PMIC's chip
ID register against the expected value. This was already being done in
the H6 version of the code.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Change-Id: Icdcf9edd6565f78cccc503922405129ac27e08a2
      0bc752c9
    • Samuel Holland's avatar
      allwinner: a64: power: Use fdt_for_each_subnode · 79b85465
      Samuel Holland authored 
      

This simplifies the code a bit. Verified to produce the same binary.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Change-Id: Ie1ec1ce2ea39c46525840906826c90a8a7eff287
      79b85465