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  1. 28 Jun, 2021 1 commit
    • Max Shvetsov's avatar
      feat(sve): enable SVE for the secure world · 0c5e7d1c
      Max Shvetsov authored 
      

Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is configured during initial setup and then uses EL3
context save/restore routine to switch between SVE configurations for
different contexts.
Reset value of CPTR_EL3 changed to be most restrictive by default.
Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
      0c5e7d1c
  3. 23 Jun, 2021 1 commit
  5. 03 Jun, 2021 1 commit
  7. 28 May, 2021 1 commit
  9. 14 May, 2021 1 commit
    • Alexei Fedorov's avatar
      fix(security): Set MDCR_EL3.MCCD bit · 12f6c064
      Alexei Fedorov authored 
      

This patch adds setting MDCR_EL3.MCCD in 'el3_arch_init_common'
macro to disable cycle counting by PMCCNTR_EL0 in EL3 when
FEAT_PMUv3p7 is implemented. This fixes failing test
'Leak PMU CYCLE counter values from EL3 on PSCI suspend SMC'
on FVP models with 'has_v8_7_pmu_extension' parameter set to
1 or 2.
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: I2ad3ef501b31ee11306f76cb5a61032ecfd0fbda
      12f6c064
  11. 21 Apr, 2021 1 commit
    • Yann Gautier's avatar
      Add PIE support for AARCH32 · 4324a14b
      Yann Gautier authored 
      

Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just
stubbed with _pie_fixup_size=0.
The changes are an adaptation for AARCH32 on what has been done for
PIE support on AARCH64.
The RELA_SECTION is redefined for AARCH32, as the created section is
.rel.dyn and the symbols are .rel*.

Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      4324a14b
  13. 20 Apr, 2021 1 commit
  15. 13 Apr, 2021 1 commit
  17. 07 Apr, 2021 1 commit
    • Max Shvetsov's avatar
      Fix: Remove save/restore of EL2 timer registers · a7cf2743
      Max Shvetsov authored 
      

Since there is a secure and non-secure version of the timer registers
there is no need to preserve their context in EL3.
With that, following registers were removed from EL3 save/restore
routine:
	cnthps_ctl_el2
	cnthps_tval_el2
	cnthps_cval_el2
	cnthvs_ctl_el2
	cnthvs_tval_el2
	cnthvs_cval_el2
	cnthp_ctl_el2
	cnthp_cval_el2
	cnthp_tval_el2
	cnthv_ctl_el2
	cnthv_cval_el2
	cnthv_tval_el2
Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b
      a7cf2743
  19. 06 Apr, 2021 1 commit
  21. 31 Mar, 2021 1 commit
  23. 24 Mar, 2021 1 commit
  25. 10 Mar, 2021 1 commit
  27. 01 Mar, 2021 1 commit
  29. 25 Feb, 2021 1 commit
  31. 24 Feb, 2021 1 commit
    • Andre Przywara's avatar
      libc: memset: Fix MISRA issues · 005415a3
      Andre Przywara authored 
      

MISRA complained about "0"s not being followed by an "U" (please note
my protest about this!) and about values not being explicitly compared
to 0 (fair enough).
Also use explicit pointer types.

Fix those issues to make the CI happy.

Change-Id: I4d11e49c14f16223a71c78b0fc3e68ba9a1382d3
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      005415a3
  33. 23 Feb, 2021 1 commit
  35. 05 Feb, 2021 1 commit
  37. 03 Feb, 2021 4 commits
  39. 29 Jan, 2021 1 commit
    • Madhukar Pappireddy's avatar
      Fix exception handlers in BL31: Use DSB to synchronize pending EA · c2d32a5f
      Madhukar Pappireddy authored 
      For SoCs which do not implement RAS, use DSB as a barrier to
synchronize pending external aborts at the entry and exit of
exception handlers. This is needed to isolate the SErrors to
appropriate context.

However, this introduces an unintended side effect as discussed
in the https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/3440


A summary of the side effect and a quick workaround is provided as
part of this patch and summarized here:

The explicit DSB at the entry of various exception vectors in BL31
for handling exceptions from lower ELs can inadvertently trigger an
SError exception in EL3 due to pending asyncrhonouus aborts in lower
ELs. This will end up being handled by serror_sp_elx in EL3 which will
ultimately panic and die.

The way to workaround is to update a flag to indicate if the exception
truly came from EL3. This flag is allocated in the cpu_context
structure. This is not a bullet proof solution to the problem at hand
because we assume the instructions following "isb" that help to update
the flag (lines 100-102 & 139-141) execute without causing further
exceptions.

Change-Id: I4d345b07d746a727459435ddd6abb37fda24a9bf
Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      c2d32a5f
  41. 21 Jan, 2021 1 commit
  43. 20 Jan, 2021 3 commits
  45. 14 Jan, 2021 1 commit
    • Heyi Guo's avatar
      lib/extensions/ras: fix bug of binary search · 0b1838a9
      Heyi Guo authored 
      

In ras_interrupt_handler(), binary search end was set to the size of
the ras_interrupt_mappings array, which would cause out of bound
access when the input intr_raw is larger than all the elements in
ras_interrupt_mappings.
Signed-off-by: default avatarHeyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Id2cff73177134b09d4d8beb596c3429b98ec5066
      0b1838a9
  47. 13 Jan, 2021 2 commits
  49. 12 Jan, 2021 1 commit
  51. 06 Jan, 2021 1 commit
    • Alexei Fedorov's avatar
      AArch64: Fix assertions in processing dynamic relocations · db9736e3
      Alexei Fedorov authored 
      

This patch provides the following changes in fixup_gdt_reloc()
function:
- Fixes assertions in processing dynamic relocations, when
relocation entries not matching R_AARCH64_RELATIVE type are found.
Linker might generate entries of relocation type R_AARCH64_NONE
(code 0), which should be ignored to make the code boot. Similar
issue was fixed in OP-TEE (see optee_os/ldelf/ta_elf_rel.c
commit 7a4dc765c133125428136a496a7644c6fec9b3c2)
- Fixes bug when "b.ge" (signed greater than or equal) condition
codes were used instead of "b.hs" (greater than or equal) for
comparison of absolute addresses.
- Adds optimisation which skips fixing Global Object Table (GOT)
entries when offset value is 0.

Change-Id: I35e34e055b7476843903859be947b883a1feb1b5
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      db9736e3
  53. 22 Dec, 2020 1 commit
    • Graeme Gregory's avatar
      PSCI: fix limit of 256 CPUs caused by cast to unsigned char · a86865ac
      Graeme Gregory authored 
      

In psci_setup.c psci_init_pwr_domain_node() takes an unsigned
char as node_idx which limits it to initialising only the first
256 CPUs. As the calling function does not check for a limit of
256 I think this is a bug so change the unsigned char to
uint16_t and change the cast from the calling site in
populate_power_domain_tree().

Also update the non_cpu_pwr_domain_node structure lock_index
to uint16_t and update the function signature for psci_lock_init()
appropriately.

Finally add a define PSCI_MAX_CPUS_INDEX to psci_private.h and add
a CASSERT to psci_setup.c to make sure PLATFORM_CORE_COUNT cannot
exceed the index value.
Signed-off-by: default avatarGraeme Gregory <graeme@nuviainc.com>
Change-Id: I9e26842277db7483fd698b46bbac62aa86e71b45
      a86865ac
  55. 18 Dec, 2020 1 commit
  57. 11 Dec, 2020 1 commit
    • Javier Almansa Sobrino's avatar
      Add support for FEAT_MTPMU for Armv8.6 · 0063dd17
      Javier Almansa Sobrino authored 
      

If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.

If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.

This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.
Signed-off-by: default avatarJavier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
      0063dd17
  59. 02 Dec, 2020 1 commit
  61. 30 Nov, 2020 1 commit
  63. 12 Nov, 2020 2 commits
  65. 20 Oct, 2020 1 commit