- 27 Jan, 2020 1 commit
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Madhukar Pappireddy authored
In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate the build to require that ARM_BL31_IN_DRAM is enabled as well. Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code cannot be reclaimed to be used for runtime data such as secondary cpu stacks. Memory map for BL31 NOBITS region also has to be created. Change-Id: Ibbc8c9499a32e63fd0957a6e254608fbf6fa90c9 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 23 Jan, 2020 1 commit
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Mark Dykes authored
This reverts commit d433bbdd. Change-Id: I46c69dce704a1ce1b50452dd4d62425c4a67f7f0
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- 22 Jan, 2020 1 commit
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Madhukar Pappireddy authored
In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate the build to require that ARM_BL31_IN_DRAM is enabled as well. Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code cannot be reclaimed to be used for runtime data such as secondary cpu stacks. Memory map for BL31 NOBITS region also has to be created. Change-Id: Ibd480f82c1dc74e9cbb54eec07d7a8fecbf25433 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 10 Jan, 2020 1 commit
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Deepika Bhavnani authored
NOTE for platform integrators: API `plat_psci_stat_get_residency()` third argument `last_cpu_idx` is changed from "signed int" to the "unsigned int" type. Issue / Trouble points 1. cpu_idx is used as mix of `unsigned int` and `signed int` in code with typecasting at some places leading to coverity issues. 2. Underlying platform API's return cpu_idx as `unsigned int` and comparison is performed with platform specific defines `PLAFORM_xxx` which is not consistent Misra Rule 10.4: The value of a complex expression of integer type may only be cast to a type that is narrower and of the same signedness as the underlying type of the expression. Based on above points, cpu_idx is kept as `unsigned int` to match the API's and low-level functions and platform defines are updated where ever required Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
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- 20 Dec, 2019 2 commits
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Paul Beesley authored
The Secure Partition Manager (SPM) prototype implementation is being removed. This is preparatory work for putting in place a dispatcher component that, in turn, enables partition managers at S-EL2 / S-EL1. This patch removes: - The core service files (std_svc/spm) - The Resource Descriptor headers (include/services) - SPRT protocol support and service definitions - SPCI protocol support and service definitions Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426 Signed-off-by: Paul Beesley <paul.beesley@arm.com> Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
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Paul Beesley authored
There are two different implementations of Secure Partition management in TF-A. One is based on the "Management Mode" (MM) design, the other is based on the Secure Partition Client Interface (SPCI) specification. Currently there is a dependency between their build flags that shouldn't exist, making further development harder than it should be. This patch removes that dependency, making the two flags function independently. Before: ENABLE_SPM=1 is required for using either implementation. By default, the SPCI-based implementation is enabled and this is overridden if SPM_MM=1. After: ENABLE_SPM=1 enables the SPCI-based implementation. SPM_MM=1 enables the MM-based implementation. The two build flags are mutually exclusive. Note that the name of the ENABLE_SPM flag remains a bit ambiguous - this will be improved in a subsequent patch. For this patch the intention was to leave the name as-is so that it is easier to track the changes that were made. Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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- 07 Nov, 2019 1 commit
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Manish Pandey authored
Earlier PIE support was enabled for all arm platforms when RESET_TO_BL31=1, but later on it was restricted only to FVP with patch SHA d4580d17 because of n1sdp platform. Now it has been verified that PIE does work for n1sdp platform also, so enabling it again for all arm platforms. Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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- 01 Aug, 2019 1 commit
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Julius Werner authored
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 26 Jun, 2019 1 commit
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Manoj Kumar authored
N1SDP platform supports RDIMMs with ECC capability. To use the ECC capability, the entire DDR memory space has to be zeroed out before enabling the ECC bits in DMC620. Zeroing out several gigabytes of memory from SCP is quite time consuming so functions are added that zeros out the DDR memory from application processor which is much faster compared to SCP. BL33 binary cannot be copied to DDR memory before enabling ECC so this is also done by TF-A from IOFPGA-DDR3 memory to main DDR4 memory after ECC is enabled. Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which the entire DDR space cannot be accessed as DRAM2 starts in base 0x8080000000. So these macros are redefined for all ARM platforms. Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
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- 15 May, 2019 1 commit
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Sami Mujawar authored
The default DRAM2 base address for Arm platforms is 0x880000000. However, on some platforms the firmware may want to move the start address to a different value. To support this introduce PLAT_ARM_DRAM2_BASE that defaults to 0x880000000; but can be overridden by a platform (e.g. in platform_def.h). Change-Id: I0d81195e06070bc98f376444b48ada2db1666e28 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
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- 23 Jan, 2019 1 commit
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Sathees Balya authored
On ARM platforms, the BL2 memory can be overlaid by BL31/BL32. The memory descriptors describing the list of executable images are created in BL2 R/W memory, which could be possibly corrupted later on by BL31/BL32 due to overlay. This patch creates a reserved location in SRAM for these descriptors and are copied over by BL2 before handing over to next BL image. Also this patch increases the PLAT_ARM_MAX_BL2_SIZE for juno when TBBR is enabled. Fixes ARM-Software/tf-issues#626 Change-Id: I755735706fa702024b4032f51ed4895b3687377f Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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- 15 Jan, 2019 1 commit
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Antonio Nino Diaz authored
From now on, platform_def.h must include any header with definitions that are platform-specific (like arm_def.h) and the included headers mustn't include back platform_def.h, and shouldn't be used by other files. Only platform_def.h should be included in other files. This will ensure that all needed definitions are present, rather than needing to include all the headers in all the definitions' headers just in case. This also prevents problems like cyclic dependencies. Change-Id: I9d3cf4d1de4b956fa035c79545222697acdaf5ca Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 07 Jan, 2019 1 commit
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Soby Mathew authored
The patch SHA 55cf015c enabled PIE support when RESET_TO_BL31=1 for all ARM platforms. But it seems n1sdp platform doesn't work with PIE support yet. Hence restrict the ENABLE_PIE=1 to fvp platform. Change-Id: If44e42528e4b0b57c69084503f346576fe0748bd Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 04 Jan, 2019 2 commits
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Even though this is not used unless SPD=tspd, only defining it when SPD_tspd is defined doesn't have any advantage and it makes it harder to read the code. Change-Id: I3d93135e05f39be071d16f8a47394a9a3ff54bc8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 17 Dec, 2018 1 commit
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Soby Mathew authored
This patch defines BL31_BASE to 0x0 when RESET_TO_BL31=1 as the executable is built with PIE support and can be loaded anywhere in SRAM for execution. Change-Id: I4007f4626322f1200a6304c9c565987d3357986c Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 27 Nov, 2018 1 commit
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Chandni Cherukuri authored
For platforms using multi-threaded CPUs, there can be upto four platform power domain levels. At present, there are three platform power domain levels that are defined for the CSS platforms. Define a fourth level 'ARM_PWR_LVL3' as well to provide support for an additional platform power domain level. Change-Id: I40cc17a10f4690a560776f504364fd7277a7e72a Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 07 Nov, 2018 1 commit
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Sandrine Bailleux authored
On AArch32, ARM_DRAM1_BASE and ARM_DRAM1_SIZE constants are currently 32-bit values (because they are suffixed with UL and the value 0x80000000 fits in a unsigned long int, i.e. a 32-bit value). When summing them up, the result overflows the maximum value that can be encoded in a 32-bit value so it wraps around and does not result in the expected value. This patch changes the suffix of these constants into ULL so that they always are 64-bit values. Change-Id: I3b19b1805e35cc7e43050458df379081b1e882d5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 01 Nov, 2018 1 commit
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Antonio Nino Diaz authored
Change-Id: I33eaee8e7c983b3042635a448cb8d689ea4e3a12 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 23 Oct, 2018 1 commit
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Antonio Nino Diaz authored
The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been fixed. The types tzc_region_attributes_t and tzc_action_t have been removed and replaced by unsigned int because it is not allowed to do logical operations on enums. Also, fix some address definitions in arm_def.h. Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 11 Oct, 2018 1 commit
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Antonio Nino Diaz authored
This file is shared between FVP and all CSS platforms. While it may be true that some definitions can be common, it doesn't make sense conceptually. For example, the stack size depends on the platform and so does the SRAM size. After removing them, there are not enough common definitions to justify having this header, so the other definitions have been moved to the platform_def.h of FVP, board_css_def.h and arm_def.h. Change-Id: Ifbf4b017227f9dfefa1a430f67d7d6baae6a4ba1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 03 Oct, 2018 1 commit
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Daniel Boulby authored
Map the initialization code for BL31 to overlap with the memory required for the secondary cores stack. Once BL31 has been initialized the memory can be remapped to RW data so that it can be used for secondary cores stacks. By moving code from .text to .text.init the size of the BL31 image is decreased by a page. Split arm_common.ld.S into two linker scripts, one for tzc_dram (arm_tzc_dram.ld.S) and one for reclaiming initialization code (arm_reclaim_init.ld.S) so that platforms can chose which memory regions they wish to include. Change-Id: I648e88f3eda1aa71765744cf34343ecda9320b32 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Remove references to removed build options. - Remove support for legacy GIC driver. - Remove support for LOAD_IMAGE_V2=0. Change-Id: I72f8c05620bdf4a682765e6e53e2c04ca749a3d5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 04 Sep, 2018 1 commit
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John Tsichritzis authored
This patch introduces the shared Mbed TLS heap optimisation for Arm platforms. The objective is the Mbed TLS heap to be shared between BL1 and BL2 so as to not allocate the heap memory twice. To achieve that, the patch introduces all the necessary helpers for implementing this optimisation. It also applies it for FVP. Change-Id: I6d85eaa1361517b7490956b2ac50f5fa0d0bb008 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 30 Aug, 2018 1 commit
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Antonio Nino Diaz authored
Change-Id: I130e35d55c474ecd80f9a825be23620d5bc1a715 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 06 Aug, 2018 1 commit
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Roberto Vargas authored
Change-Id: Idb9ba3864d6de3053260724f07172fd32c1523e0 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 01 Aug, 2018 1 commit
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Daniel Boulby authored
TF won't build since no memory region is specified for when SEPARATE_CODE_AND_RODATA=0 it still relies on the ARM_MAP_BL_RO_DATA region which is never defined for this case. Create memory region combining code and RO data for when the build flag SEPARATE_CODE_AND_RODATA=0 to fix this Change-Id: I6c129eb0833497710cce55e76b8908ce03e0a638 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 24 Jul, 2018 1 commit
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Daniel Boulby authored
Change arm_setup_page_tables() to take a variable number of memory regions. Remove coherent memory region from BL1, BL2 and BL2U as their coherent memory region doesn't contain anything and therefore has a size of 0. Add check to ensure this doesn't change without us knowing. Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 20 Jul, 2018 1 commit
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Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 20 Jun, 2018 1 commit
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Soby Mathew authored
Currently TF-A doesn't initialise CNTFRQ register in CNTCTLBase frame of the system timer. ARM ARM states that "The instance of the register in the CNTCTLBase frame must be programmed with this value as part of system initialization." The psci_arch_setup() updates the CNTFRQ system register but according to the ARM ARM, this instance of the register is independent of the memory mapped instance. This is only an issue for Normal world software which relies on the memory mapped instance rather than the system register one. This patch resolves the issue for ARM platforms. The patch also solves a related issue on Juno, wherein CNTBaseN.CNTFRQ can be written and does not reflect the value of the register in CNTCTLBase frame. Hence this patch additionally updates CNTFRQ register in the Non Secure frame of the CNTBaseN. Fixes ARM-Software/tf-issues#593 Change-Id: I09cebb6633688b34d5b1bc349fbde4751025b350 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 13 Jun, 2018 1 commit
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Sandrine Bailleux authored
The translation tables allocated for the Secure Partition do not need to be treated as a special case. They can be put amongst the other tables mapping BL31's general purpose memory. They will be mapped with the same attributes as them, which is fine. The explicit alignment constraint in BL31's linker script to pad the last page of memory allocated to the Secure Partition's translation tables is useless too, as page tables are per se pages, thus their end address is naturally aligned on a page-boundary. In fact, this patch does not change the existing behaviour. Since patch 22282bb6 ("SPM: Move all SP-related info to SP context struct"), the secure_partition.c file has been renamed into sp_xlat.c but the linker script has not been properly updated. As a result, the SP translation tables are not specifically put at the start of the xlat_table linker section, the __SP_IMAGE_XLAT_TABLES_START__/_END__ symbols have the same value, the size of the resulting mmap_region covering these xlat tables is 0 and so it is ignored. Change-Id: I4cf0a4cc090298811cca53fc9cee74df0f2b1512 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 11 Jun, 2018 1 commit
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Dimitris Papastamos authored
For the BL2_AT_EL3 configuration, move BL2 higher up to make more space for BL31. Adjust the BL31 limit to be up to BL2 base. This is because BL2 is always resident for the BL2_AT_EL3 configuration and thus we cannot overlay it with BL31. Change-Id: I71e89863ed48f5159e8b619f49c7c73b253397aa Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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- 07 Jun, 2018 1 commit
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Soby Mathew authored
The patch changes the layout of BL images in memory to enable more efficient use of available space. Previously BL31 was loaded with the expectation that BL2 memory would be reclaimed by BL32 loaded in SRAM. But with increasing memory requirements in the firmware, we can no longer fit BL32 in SRAM anymore which means the BL2 memory is not reclaimed by any runtime image. Positioning BL2 below BL1-RW and above BL31 means that the BL31 NOBITS can be overlaid on BL2 and BL1-RW. This patch also propogates the same memory layout to BL32 for AArch32 mode. The reset addresses for the following configurations are also changed : * When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode * When BL2_AT_EL3=1 for BL2 The restriction on BL31 to be only in DRAM when SPM is enabled is now removed with this change. The update to the firmware design guide for the BL memory layout is done in the following patch. Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 21 May, 2018 1 commit
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Soby Mathew authored
This patch adds soc_fw_config, tos_fw_config and nt_fw_config to the FVP. The config files are placeholders and do not have any useful bindings defined. The tos_fw_config is packaged in FIP and loaded by BL2 only if SPD=tspd. The load address of these configs are specified in tb_fw_config via new bindings defined for these configs. Currently, in FVP, the soc_fw_config and tos_fw_config is loaded in the page between BL2_BASE and ARM_SHARED_RAM. This memory was typically used for BL32 when ARM_TSP_RAM_LOCATION=tsram but since we cannot fit BL32 in that space anymore, it should be safe to use this memory for these configs. There is also a runtime check in arm_bl2_dyn_cfg_init() which ensures that this overlap doesn't happen. The previous arm_dyn_get_hwconfig_info() is modified to accept configs other than hw_config and hence renamed to arm_dyn_get_config_load_info(). The patch also corrects the definition of ARM_TB_FW_CONFIG_LIMIT to be BL2_BASE. Change-Id: I03a137d9fa1f92c862c254be808b8330cfd17a5a Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 11 May, 2018 1 commit
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Chris Kay authored
There are three calls to mmap_add_region() that always occur in arm_setup_page_tables(), and two further calls based on whether coherent memory is enabled, and whether SPM is enabled in BL31. This commit adapts the ARM_BL_REGIONS definition to match the number of calls made inside arm_setup_page_tables() so that the MAX_MMAP_REGIONS is realigned with what is actually occurring. Change-Id: I7adc05951abccf2cbd5c86280eb874911e6a1566 Signed-off-by: Chris Kay <chris.kay@arm.com>
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- 04 May, 2018 1 commit
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Jeenu Viswambharan authored
- Assign 0x10 for RAS exceptions on ARM platforms, and install EHF priority descriptor. - Call the common RAS initialisation from ARM BL31 setup. - Add empty definitions for platform error records and RAS interrupts. Change-Id: I0675f299b7840be4c83a9c7a81073a95c605dc90 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 27 Feb, 2018 1 commit
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David Cunado authored
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
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- 26 Feb, 2018 1 commit
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Soby Mathew authored
This patch modifies the bl1_platform_setup() API to load and authenticate TB_FW_CONFIG in BL1. The load address of the same is passed on to BL2 in `arg0` of entrypoint info. The fvp_io_storage.c and arm_io_storage.c also adds entries corresponding to TB_FW_CONFIG. A helper function `arm_load_tb_fw_config()` is added to load and authenticate TB_FW_CONFIG if present. Change-Id: Ie7bce667b3fad2b1a083bbcbc0a773f9f04254b1 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 18 Jan, 2018 1 commit
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Roberto Vargas authored
This patch add supports for the new API added for BL2 at EL3 for FVP. We don't have a non-TF Boot ROM for FVP, but this option can be tested setting specific parameters in the model. The bl2 image is loaded directly in memory instead of being loaded by a non-TF Boot ROM and the reset address is changed: --data cluster0.cpu0=bl2.bin@0x4001000 -C cluster0.cpu0.RVBAR=0x4001000 These parameters mean that in the cold boot path the processor will jump to BL2 again. For this reason, BL2 is loaded in dram in this case, to avoid other images reclaiming BL2 memory. Change-Id: Ieb2ff8535a9e67ccebcd8c2212cad366e7776422 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 19 Dec, 2017 1 commit
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Jeenu Viswambharan authored
With this patch, ARM platforms are expected to define the macros PLAT_ARM_SDEI_PRIVATE_EVENTS and PLAT_ARM_SDEI_SHARED_EVENTS as a list of private and shared events, respectively. This allows for individual platforms to define their own events. Change-Id: I66851fdcbff83fd9568c2777ade9eb12df284b49 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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