- 29 Jan, 2019 3 commits
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Marek Vasut authored
Allow auto-detecting E3 when RCAR_LSI is set to RCAR_AUTO. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
The macro is not used, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
This reverts commit d48536e2 , which misbehaves on R-Car H3 ES2.0. Until the reason for that misbehavior is understood, revert the commit. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 08 Jan, 2019 18 commits
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Marek Vasut authored
Update the reported Renesas version to 2.0.0, since the DDR/QoS/PFC table versions match the ones from that release. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Replace the ad-hoc implementation of delay in PWRC driver with common R-Car delay code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Rewrite the delay code from assembler to C. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add code to determine the platform timer frequency and configure the generic timer accordingly early in BL2. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Move the rcar_cpld_reset_cpu() function into header file and zap the externs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Since the interrupts are handled in EL3, dump the EL3 error registers in case an error happens. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
The reset address is programmable on the R-Car Gen3, enable it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Disable the IPMMU PV0 cache on E3 rev. 1.x . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add support for R-Car E3 silicon rev. 1.1 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add missing TARGET_NAME for the case where RCAR_LSI is set to AUTO, which is platform auto-detection. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Call the function only from architecture setup and at the end of suspend cycle instead of calling it all over the place. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable BL2 area. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Staticize the platform memory map tables as they are only used within the platform_common.c file. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Replace foo_t with struct foo. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
The CPU has cache line size of 64 Bytes, fix the cache line size. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Apply 3872fc2d ("Do not enable SVE on pre-v8.2 platforms") to R-Car Gen3 too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add missing dependency on the bl2.elf and bl31.elf into the rcar_srecord target, which uses those ELF files to generate the SRECs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Rename the H3 label to avoid confusing clang, which generates an error if the label is just H3. Rename it to RCARH3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 13 Dec, 2018 1 commit
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Marek Vasut authored
As suggested, pass the FDT to BL 33 via x1 instead of x3 , to be consistent with the other platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 06 Dec, 2018 9 commits
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Marek Vasut authored
Generate a /reserved-memory node for FCNL in the DT passed to subsequent stages, so they will know how the FCNL is configured. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Generate /compatible string for the platform, so that the subsequent stages know which platform they are running on. This could be useful when ie. building U-Boot that contains DTs for multiple platforms and can thus decide on which platform it is running. This would ultimately allow single bootloader binary for all Gen3 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Pass DTB containing DRAM layout from BL2 to BL33 via register x3, so that the BL33 can simply consume it and get accurate DRAM layout info. BL33 is in most usecases U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Use array of start-size tuples for the DRAM banks and call single function which iterates over this array to report the DRAM info. This is in preparation for expanding this to generate FDT for the next stage. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Print the DRAM configuration only after the DRAM was initialized. This will be useful when deduplicating code populating FDT passed to U-Boot, since it will contain the same macros as bl2_advertise_dram_size(). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Make the DRAM configuration debug print consistent for all supported SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
There is nothing preventing H3 older than v3.0 from printing the DRAM configuration, just like v3.0 and newer. Drop the check and let all H3 revisions print DRAM configuration in BL2. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
RCAR_DRAM_DDR3L_MEMCONF = 2 means E3 with 1GBx4 memory configuration. Add debug print for this configuration for completeness sake. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Just move the DRAM layout information into separate function, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 20 Nov, 2018 1 commit
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Jorge Ramirez-Ortiz authored
RCAR_RPC_HYPERFLASH_LOCKED can be set to 0 as a build option if the user needs to allow u-boot to reprogram the ATF firmware using a FIP image (as a faster alternative of toggling numerous DIP switches on the board and using ascii-xfer of srec files) The code being controlled with this commit should only be re-enabled for debugging (_never_ on a product release) Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
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- 08 Nov, 2018 1 commit
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 06 Nov, 2018 2 commits
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ldts authored
Target builds but has not been tested. Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>
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ldts authored
Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>
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- 17 Oct, 2018 2 commits
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Jorge Ramirez-Ortiz authored
- ddr - pfc [pin function controller] - qos [bandwidth] checkpatch.pl is generating too many errors.
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Jorge Ramirez-Ortiz authored
Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
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