- 17 Aug, 2018 5 commits
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Dimitris Papastamos authored
DTC: Add recommended device tree compiler version
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Sathees Balya authored
Change-Id: Ice87052e41a24b0ede5610467e12941ae1d886e0 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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Dimitris Papastamos authored
rpi3: Remove dependencies on Arm platform code
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Dimitris Papastamos authored
Fix typo in documentation page title
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Dimitris Papastamos authored
Console: Use callee-saved registers
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- 15 Aug, 2018 4 commits
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John Tsichritzis authored
Change-Id: I426ffc8717757e35e556f675162a729ba095b7d5 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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Antonio Nino Diaz authored
The Raspberry Pi 3 port doesn't actually depend on any Arm platform code, so the dependencies can be removed. Change-Id: Ic2f47f5001bebde3862815b1d880a169d82b3f65 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Sathees Balya authored
This allows the console drivers to be implemented in C Change-Id: Ibac859c4bcef0e92a0dcacc6b58ac19bc69b8342 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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Dimitris Papastamos authored
Replace stdio.h functions by TF functions
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- 13 Aug, 2018 6 commits
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Dimitris Papastamos authored
readme: Add information about the TF-A IRC channel
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Dimitris Papastamos authored
cci: Use dsb to wait before reading status register
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Roberto Vargas authored
The CCI500 TRM explicitily requires completion of the write operation before the read operation, and it is not guaranteed by dmb but it is dsb. Change-Id: Ieeaa0d1a4b8fcb87108dea9b6de03d9c8a150829 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Dimitris Papastamos authored
Add support for moving libraries to ROM
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Dimitris Papastamos authored
xlat v2: Support EL2 translation regime
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Dimitris Papastamos authored
mmc: Fix warning about usage of uninitialized variable
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- 10 Aug, 2018 17 commits
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Antonio Nino Diaz authored
Because of -Werror, this causes a build error. Change-Id: I37a8c4bbfe3f2ced5e17981a2814985919ad483b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I3d16b247a0fa457e6293e2d2c4503dfde1e51c1d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I1bb310e1b05968d30b28913c4011c0601e1ae64e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The translation library is useful elsewhere. Even though this repository doesn't exercise the EL2 support of the library, it is better to have it here as well to make it easier to maintain. enable_mmu_secure() and enable_mmu_direct() have been deprecated. The functions are still present, but they are behind ERROR_DEPRECATED and they call the new functions enable_mmu_svc_mon() and enable_mmu_direct_svc_mon(). Change-Id: I13ad10cd048d9cc2d55e0fff9a5133671b67dcba Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Dimitris Papastamos authored
Migrate mmc
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Haojian Zhuang authored
Remove emmc framework from maintain list. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Replace emmc framework by mmc framework. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Migrate from emmc framework to mmc framework. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Migrate to mmc framework. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Migrate dw_mmc driver from emmc framework to mmc framework. The emmc framework will be abandoned. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
It should set buswidth and speed of mmc controller before accessing mmc. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
DMA is always used in mmc driver. So the buffer address should always follow the DMA limitation. There're same requirement in mmc_read_blocks()/mmc_write_blocks() on parameter buf. Since parameter buf comes from io_block driver, it's already handled in io_block driver. At here, just make the minimum address alignment on 16 chars. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
mmc_read_blocks()/mmc_write_blocks() derived from io_block_ops_t type. It means that lba param should be integer type, not unsigned integer type. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Sending CMD8 before CMD1 just causes to fetch data failure in eMMC. Check whether it's eMMC first. If it's eMMC, send CMD1 command instead. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Dimitris Papastamos authored
mmc: add required delays when retrying commands
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Antonio Nino Diaz authored
Functions provided by stdio.h such as printf and sprintf are available in the codebase, but they add a lot of code to the final image if they are used: - AArch64: ~4KB - AArch32: ~2KB in T32, ~3KB in A32 tf_printf and tf_snprintf are a lot more simple, but it is preferable to use them when possible because they are also used in common code. Change-Id: Id09fd2b486198fe3d79276e2c27931595b7ba60e Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Ia3a159444e638f63de7dc5a6a4b76169c757188a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 09 Aug, 2018 1 commit
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Dimitris Papastamos authored
xlat v2: Cleanup and dcache coherency bug fix
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- 07 Aug, 2018 1 commit
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Antonio Nino Diaz authored
During cold boot, the initial translation tables are created with data caches disabled, so all modifications go to memory directly. After the MMU is enabled and data cache is enabled, any modification to the tables goes to data cache, and eventually may get flushed to memory. If CPU0 modifies the tables while CPU1 is off, CPU0 will have the modified tables in its data cache. When CPU1 is powered on, the MMU is enabled, then it enables coherency, and then it enables the data cache. Until this is done, CPU1 isn't in coherency, and the translation tables it sees can be outdated if CPU0 still has some modified entries in its data cache. This can be a problem in some cases. For example, the warm boot code uses only the tables mapped during cold boot, which don't normally change. However, if they are modified (and a RO page is made RW, or a XN page is made executable) the CPU will see the old attributes and crash when it tries to access it. This doesn't happen in systems with HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY. In these systems, the data cache is enabled at the same time as the MMU. As soon as this happens, the CPU is in coherency. There was an attempt of a fix in psci_helpers.S, but it didn't solve the problem. That code has been deleted. The code was introduced in commit <26441030 > ("Invalidate TLB entries during warm boot"). Now, during a map or unmap operation, the memory associated to each modified table is flushed. Traversing a table will also flush it's memory, as there is no way to tell in the current implementation if the table that has been traversed has also been modified. Change-Id: I4b520bca27502f1018878061bc5fb82af740bb92 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 06 Aug, 2018 4 commits
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Dimitris Papastamos authored
cci: Wait before reading status register
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Roberto Vargas authored
Change-Id: Idb9ba3864d6de3053260724f07172fd32c1523e0 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Dimitris Papastamos authored
Add support for Arm System Guidance for Mobile fixed virtual platform
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Antonio Nino Diaz authored
Changed the names for consistency with the rest of the library. Introduced new helpers that manipulate the active translation tables context. Change-Id: Icaca56b67fcf6a96e88aa3c7e47411162e8e6856 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 03 Aug, 2018 2 commits
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Nariman Poushin authored
Add support for System Guidance for Mobile platform SGM775 Change-Id: I2442a50caae8f597e5e5949cd48f695cf75d9653 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
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Deepak Pandey authored
In css platforms where the cpu/cluster management is done by the hardware, software does need to issue certain scmi requests. This patch wraps those scmi calls around the HW_ASSISTED_COHERENCY build option to remove them on platforms that have this hardware support. Change-Id: Ie818e234484ef18549aa7f977aef5c3f0fc26c27 Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
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