GitLab

This patch avoids the problem of crash reporting mechanism accessing
global data in BSS by 'plat_print_gic_regs' for FVP platforms. Earlier
it depended on the global 'plat_config' object for the GIC Base address
in FVP platforms which would have caused exception if it were accessed
before the BSS was initialized. It is now fixed by dynamically
querying the V2M_SYS_ID to find the FVP model type and accordingly
selecting the appropriate GIC Base address.

This patch also fixes the 'plat_print_gic_regs' to use the correct GIC
Distributor base address for printing GICD_IS_PENDR register values
for both Juno and FVP platforms.

Fixes ARM-Software/tf-issues#236

Change-Id: I545c7b908b3111419bf27db0575ce86acf86784b

Dispatcher for OPTEE from Linaro SWG

Adds a dispatcher for OP-TEE based on the test secure payload
dispatcher.

Fixes arm-software/tf-issues#239

Initializes SCTLR_EL1 based on MODE_RW bit in SPSR for the entry
point. The RES1 bits for SCTLR_EL1 differs for Aarch64 and Aarch32
mode.

Add support for specifying pre-built BL binaries in Makefile

This patch adds support for supplying pre-built BL binaries for BL2,
BL3-1 and BL3-2 during trusted firmware build. Specifying BLx = <path_to_BLx>
in the build command line, where 'x' is any one of BL2, BL3-1 or BL3-2, will
skip building that BL stage from source and include the specified binary in
final fip image.

This patch also makes BL3-3 binary for FIP optional depending on the
value of 'NEED_BL33' flag which is defined by the platform.

Fixes ARM-software/tf-issues#244
Fixes ARM-software/tf-issues#245

Change-Id: I3ebe1d4901f8b857e8bb51372290978a3323bfe7

Documentation for version 1.0

Fix minor issues in user guide

Final updates to readme.md and change-log.md for ARM Trusted
Firmware version 1.0. Also increment the version in the Makefile.

Change-Id: I00fe1016c8b936834bbf7bbba7aab07f51261bbb

*   Fix broken link to SCP download.

*   Remove requirement to install `ia32-libs`. This package is no
    longer available in current versions of Ubuntu and is no
    longer required when using the Linaro toolchain.

Change-Id: I9823d535a1d69136685754b7707b73e1eef0978d

Miscellaneous documentation fixes

This patch gathers miscellaneous minor fixes to the documentation, and comments
in the source code.

Change-Id: I631e3dda5abafa2d90f464edaee069a1e58b751b
Co-Authored-By: Soby Mathew <soby.mathew@arm.com>
Co-Authored-By: Dan Handley <dan.handley@arm.com>

Add information about Juno in firmware-design.md

This patch reorganizes the firmware design guide to add information about the
port of the ARM Trusted Firmware to the Juno ARM development platform.

Change-Id: I0b80e2e7a35ccad1af2e971506cfb7fe505f8b84

Fix reset to BL3-1 instructions in user guide, part 2

Add Juno instructions to user guide

This patch makes the Trusted Firmware build instructions in the
user guide platform independent.

FVP specific instructions have been grouped together under a new
section dedicated to FVP.

Juno specific instructions to build and run the Trusted Firmware,
UEFI and Linux have been added.

Change-Id: I9bfb1b9d732b1f73abbe29f68ac931e1773a4fd5

Fix the instructions for resetting to the BL3-1 entrypoint in the
user guide. The BL3-1 and BL3-2 image locations changed in the fix
to ARM-software/tf-issues#100 (commit 186c1d4b). This is distinct
from the similar issue fixed in commit bfb1dd51.

Also clarify the dependence on the FVP_SHARED_DATA_LOCATION and
FVP_TSP_RAM_LOCATION build options, and tidy up the "Notes
regarding Base FVP configuration options" section.

Change-Id: I6b03452a71f0c69efa169852712bcb184242696e

Move up dependency versions in user guide

Rationalize UART usage among different BL stages

This patch changes the UART port assignment for various BL stages
so as to make it consistent on the platform ports. The BL1, BL2 and
BL3-1 now uses UART0 on the FVP port and SoC UART0 on the Juno port.
The BL3-2 uses UART2 on the FVP port and FPGA UART0 on the Juno
port.

This provides an interim fix to ARM-software/tf-issues#220 until
support is added for changing the UART port for a BL image between
cold boot and runtime.

Change-Id: Iae5faea90be3d59e41e597b34a902f93e737505a

Move up the version numbers of the following Trusted Firmware
dependencies in the user guide:

*   Foundation and Base FVPs (latest publically available
    versions).

*   EDK2 implementation. The guide now uses the latest version from
    https://github.com/ARM-software/edk2.git. This requires the
    `iasl` package to also be installed.

*   Linux kernel. The guide now uses the latest version from
    https://github.com/ARM-software/linux.git.

*   Linaro OpenEmbedded file system.

*   ARM Development Studio 5.

Change-Id: I95bb863a61e47b9ef8be3d110f7087375ee78add

Add support for Juno in Trusted Firmware

This patch removes the PRIMARY_CPU definition hardcoded in the
Juno port. Instead, the primary CPU is obtained at runtime by
reading the SCC General Purpose Register 1 (GPR_1), whose value
is copied by the SCP into shared memory during the boot process.

Change-Id: I3981daa92eb7142250712274cf7f655b219837f5

This patch adds the Juno platform specific handlers for PSCI
SYSTEM_OFF and SYSTEM_RESET operations.

Change-Id: Ie389adead533ec2314af44d721b4d0f306147c7d

This patch implements the TSP on Juno. It executes from on-chip Trusted
SRAM.

Also, the other bootloader images (i.e. BL1 R/W, BL2 and BL3-1) have
been moved around. The reason is, although there was enough space
overall to store the TSP in SRAM, there was no contiguous free chunk
of SRAM big enough to hold it.

This patch keeps the overall memory layout (i.e. keeping BL1 R/W at
the bottom, BL2 at the top and BL3-1 in between) but moves the base
addresses of all the bootloader images in such a way that:
 - memory fragmentation is reduced enough to fit BL3-2 in;
 - new base addresses are suitable for release builds as well as debug
   ones;
 - each image has a few extra kilobytes for future growth.
   BL3-1 and BL3-2 are the images which received the biggest allocations
   since they will most probably grow the most.

This patch also adds instruction synchronization barriers around the code which
handles the timer interrupt in the TSP. This ensures that the interrupt is not
acknowledged after or EOIed before it is deactivated at the peripheral.

Change-Id: I1c5b51858700027ee283ac85d18e06863a27c72e

This patch adds support for PSCI CPU_OFF and CPU_SUSPEND APIs to the Juno port
of the ARM Trusted Firmware. The maximum affinity level that can be suspended is
the cluster level (affinity level 1). Support for suspending the system level is
not present.

Change-Id: Ie2c9da0acd7d1b0d5ac64940cdf40347153e52c8

This patch adds the initial port of the ARM Trusted Firmware on the Juno
development platform. This port does not support a BL3-2 image or any PSCI APIs
apart from PSCI_VERSION and PSCI_CPU_ON. It enables workarounds for selected
Cortex-A57 (#806969 & #813420) errata and implements the workaround for a Juno
platform errata (Defect id 831273).

Change-Id: Ib3d92df3af53820cfbb2977582ed0d7abf6ef893

FVP: Update device trees to match cpuidle driver

Implement the CPU Specific operations framework v3

This patch updates the representation of idle tables and cpu/cluster topology in
the device tree source files for the FVP to what the latest cpuidle driver in
Linux expects. The device tree binaries have also been updated.

Change-Id: If0668b96234f65aa0435fba52f288c9378bd8824

This patch adds documentation for CPU specific abstraction in the firmware-
design.md and adds a new document cpu-errata-workarounds.md to describe
the cpu errata workaround build flags.

Change-Id: Ia08c2fec0b868a0a107d0264e87a60182797a1bd

This patch adds workarounds for selected errata which affect the Cortex-A57 r0p0
part. Each workaround has a build time flag which should be used by the platform
port to enable or disable the corresponding workaround. The workarounds are
disabled by default. An assertion is raised if the platform enables a workaround
which does not match the CPU revision at runtime.

Change-Id: I9ae96b01c6ff733d04dc733bd4e67dbf77b29fb0

This patch adds handlers for dumping Cortex-A57 and Cortex-A53 specific register
state to the CPU specific operations framework. The contents of CPUECTLR_EL1 are
dumped currently.

Change-Id: I63d3dbfc4ac52fef5e25a8cf6b937c6f0975c8ab

This patch adds CPU core and cluster power down sequences to the CPU specific
operations framework introduced in a earlier patch. Cortex-A53, Cortex-A57 and
generic AEM sequences have been added. The latter is suitable for the
Foundation and Base AEM FVPs. A pointer to each CPU's operations structure is
saved in the per-cpu data so that it can be easily accessed during power down
seqeunces.

An optional platform API has been introduced to allow a platform to disable the
Accelerator Coherency Port (ACP) during a cluster power down sequence. The weak
definition of this function (plat_disable_acp()) does not take any action. It
should be overriden with a strong definition if the ACP is present on a
platform.

Change-Id: I8d09bd40d2f528a28d2d3f19b77101178778685d

This patch adds an optional platform API (plat_reset_handler) which allows the
platform to perform any actions immediately after a cold or warm reset
e.g. implement errata workarounds. The function is called with MMU and caches
turned off. This API is weakly defined and does nothing by default but can be
overriden by a platform with a strong definition.

Change-Id: Ib0acdccbd24bc756528a8bd647df21e8d59707ff

This patch introduces a framework which will allow CPUs to perform
implementation defined actions after a CPU reset, during a CPU or cluster power
down, and when a crash occurs. CPU specific reset handlers have been implemented
in this patch. Other handlers will be implemented in subsequent patches.

Also moved cpu_helpers.S to the new directory lib/cpus/aarch64/.

Change-Id: I1ca1bade4d101d11a898fb30fea2669f9b37b956

This patch provides a workaround for the ASM_ASSERT label issue
and also reworks the use of labels in assembly macros.
If the caller of the ASM_ASSERT macro happened to use the
label '1' to jump past the ASM_ASSERT macro, it would not have
worked since the ASM_ASSERT macro internally used the same label.
Hence, as a workaround, this patch makes the label a high
number in the expectation that the caller will never use it.

Also updated the other assembly macros using numerical labels to
named lables.

Change-Id: Iec892359db84f2391ad2a83a92141c4d7049776a

This patch implements the following cleanups in PSCI generic code:

1. It reworks the affinity level specific handlers in the PSCI implementation
   such that.

   a. Usage of the 'rc' local variable is restricted to only where it is
      absolutely needed

   b. 'plat_state' local variable is defined only when a direct invocation of
      plat_get_phys_state() does not suffice.

   c. If a platform handler is not registered then the level specific handler
      returns early.

2. It limits the use of the mpidr_aff_map_nodes_t typedef to declaration of
   arrays of the type instead of using it in function prototypes as well.

3. It removes dangling declarations of __psci_cpu_off() and
   __psci_cpu_suspend(). The definitions of these functions were removed in
   earlier patches.

Change-Id: I51e851967c148be9c2eeda3a3c41878f7b4d6978

This patch reworks FVP port's power management implementation to perform
platform actions only when the platform exported hook is invoked for the highest
affinity level to enter/exit the OFF state.

For example, during a CPU_OFF operation, fvp_affinst_off() is called twice: for
affinity level 0 and affinity level 1 (in that order). CPU specific operations
are deferred until the next invocation if it is determined through a call to
psci_get_max_phys_off_afflvl() that this is CPU is the last in the cluster.

Similarly, during power up if the CPU is the first in the cluster, both CPU and
cluster specific operations are performed when fvp_affinst_on_finish() is
invoked for affinity level 1. Earlier, they were done across the two invocations
of the handler.

Change-Id: I4288ed3ba1385db36a69cc2e598deb219f209b8a