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  1. 22 Mar, 2020 3 commits
  3. 19 Mar, 2020 3 commits
  5. 11 Mar, 2020 6 commits
    • Pritesh Raithatha's avatar
      Tegra: smmu: remove context save sequence · a391d494
      Pritesh Raithatha authored 
      

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.

This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.

Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: default avatarPritesh Raithatha <praithatha@nvidia.com>
      a391d494
    • Varun Wadekar's avatar
      Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194 · e9044480
      Varun Wadekar authored 
      

This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, was
incorrect.

Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e9044480
    • Pritesh Raithatha's avatar
      Tegra194: memctrl: lock some more MC SID security configs · de3fd9b3
      Pritesh Raithatha authored 
      

The platform code already contains the initial set of MC SID
security configs to be locked during boot. This patch adds some
more configs to the list. Since the reset value of these registers
is already as per expectations, there is no need to change it.

MC SID security configs
- PTCR,
- MIU6R, MIU6W, MIU7R, MIU7W,
- MPCORER, MPCOREW,
- NVDEC1SRD, NVDEC1SRD1, NVDEC1SWR.

Change-Id: Ia9a1f6a6b6d34fb2787298651f7a4792a40b88ab
Signed-off-by: default avatarPritesh Raithatha <praithatha@nvidia.com>
      de3fd9b3
    • Jeetesh Burman's avatar
      Tegra194: add SE support to generate SHA256 of TZRAM · 029dd14e
      Jeetesh Burman authored 
      

The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store to PMC scratch registers.

Change-Id: I04cc0eb7f54c69d64b6c34fc2ff62e4cfbdd43b2
Signed-off-by: default avatarJeetesh Burman <jburman@nvidia.com>
      029dd14e
    • Jeetesh Burman's avatar
      Tegra194: store TZDRAM base/size to scratch registers · 2ac7b223
      Jeetesh Burman authored 
      

This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.

Change-Id: I2f5fd11c87804d20e2698de33be977991c9f6f33
Signed-off-by: default avatarJeetesh Burman <jburman@nvidia.com>
      2ac7b223
    • kalyani chidambaram's avatar
      Tegra194: fix warnings for extra parentheses · 6dbe1c8f
      kalyani chidambaram authored 
      

armclang displays warnings for extra parentheses, leading to
build failures as warnings are treated as errors.
This patch removes the extra parentheses to fix this issue.

Change-Id: Id2fd6a3086590436eecabc55502f40752a018131
Signed-off-by: default avatarKalyani Chidambaram <kalyanic@nvidia.com>
      6dbe1c8f
  7. 09 Mar, 2020 2 commits
    • Pravin's avatar
      Tegra194: memctrl: add support for MIU4 and MIU5 · a69a30ff
      Pravin authored 
      

This patch adds support for memqual miu 4,5.

The MEMQUAL engine has miu0 to miu7 in which miu6 and
miu7 is hardwired to bypass SMMU. So only miu0 to miu5
support is provided.

Change-Id: Ib350334eec521e65f395f1c3205e2cdaf464ebea
Signed-off-by: default avatarPravin <pt@nvidia.com>
      a69a30ff
    • Stefan Kristiansson's avatar
      Tegra194: memctrl: remove support to reconfigure MSS · 4b74f6d2
      Stefan Kristiansson authored 
      

As bpmp-fw is running at the same time as ATF, and
the mss client reconfiguration sequence involves performing
a hot flush resets on bpmp, there is a chance that bpmp-fw is
trying to perform accesses while the hot flush is active.

Therefore, the mss client reconfigure has been moved to
System Suspend resume fw and bootloader, and it can be
removed from here.

Change-Id: I34019ad12abea9681f5e180af6bc86f2c4c6fc74
Signed-off-by: default avatarStefan Kristiansson <stefank@nvidia.com>
      4b74f6d2
  9. 25 Feb, 2020 3 commits
  11. 20 Feb, 2020 2 commits
    • Varun Wadekar's avatar
      Tegra: handler to check support for System Suspend · 5d52aea8
      Varun Wadekar authored 
      

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".

This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".

Original change by: kalyani chidambaram <kalyanic@nvidia.com>

Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5d52aea8
    • Pritesh Raithatha's avatar
      Tegra194: memctrl: lock mc stream id security config · 56e7d6a7
      Pritesh Raithatha authored 
      

This patch locks most of the stream id security config registers as
per HW guidance.

This patch keeps the stream id configs unlocked for the following
clients, to allow some platforms to still function, until they make
the transition to the latest guidance.

- ISPRA
- ISPFALR
- ISPFALW
- ISPWA
- ISPWA1
- ISPWB
- XUSB_DEVR
- XUSB_DEVW
- XUSB_HOSTR
- XUSB_HOSTW
- VIW
- VIFALR
- VIFALW

Change-Id: I66192b228a0a237035938f498babc0325764d5df
Signed-off-by: default avatarPritesh Raithatha <praithatha@nvidia.com>
      56e7d6a7
  13. 05 Feb, 2020 1 commit
  15. 31 Jan, 2020 4 commits
    • Varun Wadekar's avatar
      Tegra194: remove support for simulated system suspend · 8ad1e475
      Varun Wadekar authored 
      

This patch removes support for simulated system suspend for Tegra194
platforms as we have actual silicon platforms that support this
feature now.

Change-Id: I9ed1b002886fed7bbc3d890a82d6cad67e900bae
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8ad1e475
    • Varun Wadekar's avatar
      Tegra194: mce: fix multiple MISRA issues · 4a232d5b
      Varun Wadekar authored 
      

This patch fixes violations of the following MISRA rules

* Rule 8.5  "An external object or function shall be declared once in
             one and only one file"
* Rule 10.3 "The value of an expression shall not be assigned to an
             object with a narrower essential type or of a different
             esential type category"

Change-Id: I4314cd4fea0a4adc6665868dd31e619b4f367e14
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      4a232d5b
    • Varun Wadekar's avatar
      Tegra194: se: fix multiple MISRA issues · 8d4107f0
      Varun Wadekar authored 
      

This patch fixes violations for the following MISRA rules

* Rule 8.4  "A compatible declaration shall be visible when an object or
             function with external linkage is defined"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.6 "Both operands of an operator in which the usual arithmetic
             conversions are perdormed shall have the same essential type
             category"
* Rule 17.7 "The value returned by a function having non-void return
             type shall be used"

Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8d4107f0
    • Varun Wadekar's avatar
      Tegra: remove weakly defined PSCI platform handlers · e44f86ef
      Varun Wadekar authored 
      

This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e44f86ef
  17. 28 Jan, 2020 2 commits
    • Madhukar Pappireddy's avatar
      Enable -Wredundant-decls warning check · ca661a00
      Madhukar Pappireddy authored 
      

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      ca661a00
    • Varun Wadekar's avatar
      Tegra194: enable spe-console functionality · ffd58cca
      Varun Wadekar authored 
      

This patch enables the config to switch to the console provided
by the SPE firmware.

Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ffd58cca
  19. 23 Jan, 2020 14 commits