- 21 May, 2021 1 commit
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Igor Opaniuk authored
In iMX8MM it is possible to have two copies of bootloader in SD/eMMC and switch between them. The switch is triggered either by the BootROM in case the bootloader image is faulty OR can be enforced by the user. To trigger that switch the PERSIST_SECONDARY_BOOT bit should be set in GPR10 SRC register. As the bit is retained after WARM reset, that permits to control BootROM behavior regarding what boot image it will boot after reset: primary or secondary. This is useful for reliable bootloader A/B updates, as it permits switching between two copies of bootloader at different offsets of the same storage. If the PERSIST_SECONDARY_BOOT is 0, the boot ROM uses address 0x8400 for the primary image. If the PERSIST_SECONDARY_BOOT is 1, the boot ROM reads that secondary image table from address 0x8200 on the boot media and uses the address specified in the table for the secondary image. Secondary Image Table contains the sector of secondary bootloader image, exluding the offset to that image (explained below in the note). To generate the Secondary Image Table, use e.g.: $ printf '\x0\x0\x0\x0\x0\x0\x0\x0\x33\x22\x11' '\x00\x00\x10\x0\x0\x00\x0\x0\x0' > /tmp/sit.bin $ hexdump -vC /tmp/sit.bin 00000000 00 00 00 00 00000004 00 00 00 00 00000008 33 22 11 00 <--- This is the "tag" 0000000c 00 10 00 00 <--- This is the "firstSectorNumber" 00000010 00 00 00 00 You can also use NXP script from [1][2] imx-mkimage tool for SIT generation. Note that the firstSectorNumber is NOT the offset of the IVT, but an offset of the IVT decremented by Image Vector Table offset (Table 6-25. Image Vector Table Offset and Initial Load Region Size for iMX8MM/MQ), so for secondary SPL copy at offset 0x1042 sectors, firstSectorNumber must be 0x1000 (0x42 sectors * 512 = 0x8400 bytes offset). In order to test redundant boot board should be closed and SD/MMC manufacture mode disabled, as secondary boot is not supported in the SD/MMC manufacture mode, which can be disabled by blowing DISABLE_SDMMC_MFG (example for iMX8MM): > fuse prog -y 2 1 0x00800000 For additional details check i.MX 8M Mini Apllication Processor Reference Manual, 6.1.5.4.5 Redundant boot support for expansion device chapter. [1] https://source.codeaurora.org/external/imx/imx-mkimage/ [2] scripts/gen_sit.sh Change-Id: I0a5cea7295a4197f6c89183d74b4011cada52d4c Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
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- 23 Mar, 2021 6 commits
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Ying-Chun Liu (PaulLiu) authored
Adds bl2 with FIP to the build required for mbed Linux booting where we do: BootROM -> SPL -> BL2 -> OPTEE -> u-boot If NEED_BL2 is specified then BL2 will be built and BL31 will have its address range modified upwards to accommodate. BL31 must be loaded from a FIP in this case. If NEED_BL2 is not specified then the current BL31 boot flow is unaffected and u-boot SPL will load and execute BL31 directly. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: I655343b3b689b1fc57cfbedda4d3dc2fbd549a96
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Ying-Chun Liu (PaulLiu) authored
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: I0557ce6d0aa5ab321cac1ee25280b96762024396
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Ying-Chun Liu (PaulLiu) authored
This patch enables Trusted Boot on the i.MX8MM with BL2 doing image verification from a FIP prior to hand-over to BL31. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: I3c22783a5c49544d0bace8ef3724784b9b7cc64a
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Ying-Chun Liu (PaulLiu) authored
Adds a number of definitions consistent with the established WaRP7 equivalents specifying number of io_handles and block devices. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: If1d7ef1ad3ac3dfc860f949392c7534ce8d206e3
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Ying-Chun Liu (PaulLiu) authored
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: I9833a54d0938d70886ac88b1922b17edf1dee8e0
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Ying-Chun Liu (PaulLiu) authored
Allows for exporting of FIP related methods cleanly in a private header. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: I8523f1370312ed22ff7ca710cd916be52f725e3c
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- 09 Oct, 2020 1 commit
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Jimmy Brisson authored
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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- 20 Aug, 2020 1 commit
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Jacky Bai authored
CPU hotplug & cpuidle have some race condition when doing CPU hotplug stress test. different CPU cores have the chance to access the same GPC register(A53_AD), so lock is necessary to do exlusive access. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I1296592e05fa78429c3f0fac066951521db755e3
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- 19 Aug, 2020 2 commits
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Jacky Bai authored
The number of gpc imr mask reg & the offset is different on some SOC, so correct it & replace the magic number with macro define. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ic701675cdd92e043dcd7f06722f2e871068aec74
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Jacky Bai authored
Keep A53 PLAT(SCU) power domain on in wait mode(ret). RBC count only need to be set in PLAT OFF mode, so change it accordingly. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ie55e25c8210d298506fc4dca7a9653583db45e0c
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- 06 Aug, 2020 1 commit
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Peng Fan authored
Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor could use SDEI to do hypervisor management, after physical IRQ has been disabled routing. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I5fd697fee22df151e13d0f1335e8ac8a7bae6189
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- 22 Jul, 2020 1 commit
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Peng Fan authored
Implement IMX_SIP_AARCH32 to let AArch64 Bootloader could issue SIP call to switch to AArch32 mode to run OS. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I38b04ef909a6dbfba5ded12a7bb6e799a3935a66
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- 10 Jul, 2020 2 commits
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Jacky Bai authored
The i.MX 8MP Media Applications Processor is part of the growing i.MX8M family targeting the consumer and industrial market. It brings an effective Machine Learning and AI accelerator that enables a new class of applications. It is built in 14LPP to achieve both high performance and low power consumption and relies on a powerful fully coherent core complex based on a quad core Arm Cortex-A53 cluster and Cortex-M7 low-power coprocessor, audio digital signal processor, machine learning and graphics accelerators. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I98311ebc32bee20af05031492e9fc24d06e55f4a
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Jacky Bai authored
Although the GPC provides the similar functions for all the i.MX8M SoC family, the HW register offset and bit defines still have some slight difference, so move the hw reg offset & most of the bitfield defines in 'gpc_reg.h' that is specific to each SoC. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I291c435fe98c2f6e6ff8fe0c715ff3a83daa6a0f
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- 22 May, 2020 1 commit
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Jacky Bai authored
Add imx8mn basic support Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ibdfcc87700bfaf980e429f3a5fa08515218ae78d
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- 19 May, 2020 1 commit
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Manish V Badarkhe authored
CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c and tbbr_cot_bl2.c respectively. Common CoT used across BL1 and BL2 are moved to tbbr_cot_common.c. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5
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- 30 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 23 Mar, 2020 1 commit
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Igor Opaniuk authored
1. This removes hardcoded iomux/clk/addr configuration for debug uart, provides possibility (as a workaround, till that information isn't provided via DT) to set this configuration during compile time via IMX_DEBUG_UART build flag. Also for Colibri i.MX8QXP different pinmux configuration is applied for UART3, FLEXCAN2_RX/TX pads are muxed to ADMA_UART3_RX/TX. 2. Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A35 doesn't make sense (since UART pinmux/clock configuration is applied for UART only when DEBUG_CONSOLE_A35 is enabled. Check similar commit for i.MX8QM 98a69dfd ("plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE")). Usage: $ make PLAT=imx8qx IMX_DEBUG_UART=3 DEBUG_CONSOLE=1 bl31 Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I5d04939b2e8ee1a5f4b2f3c6241977d3c6e91760
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- 16 Mar, 2020 3 commits
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Igor Opaniuk authored
Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A53 doesn't make sense (since UART pinmux/clock configuration is applied for UART only when DEBUG_CONSOLE_A53 is enabled). Enable DEBUG_CONSOLE_A53 if DEBUG_CONSOLE is enabled. Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I8ca411d5544658b9bcc39e5340ec042c51088b96
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Igor Opaniuk authored
This removes hardcoded iomux/clk/addr configuration for debug uart, provides possibility (as a workaround, till that information isn't provided via DT) to set this configuration during compile time via IMX_DEBUG_UART build flag. Usage: $ make PLAT=imx8qm IMX_DEBUG_UART=1 bl31 Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: Ib5f5dd81ba0c8ad2b2dc5647ec75629072f511c5
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Igor Opaniuk authored
This fixes shift overflow errors, when compiled with CONSOLE_DEBUG support: plat/imx/common/include/imx8_iomux.h:11:35: error: result of ‘1 << 31’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=] Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I0488e22c30314ba27caabc5c767164baa1e8004c
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- 10 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 05 Mar, 2020 2 commits
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Igor Opaniuk authored
Some boards (f.e. Verdin i.MX8M Mini) use different UART base address for serial debug output, so make this value configurable (as a build option). Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I988492ccecbc3f64a5153b381c4a97b8a0181f52
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Andre Przywara authored
Since commit ac71344e we have the UART base address in the generic console_t structure. For most platforms the platform-specific struct console is gone, so we *must* use the embedded base address, since there is no storage behind the generic console_t anymore. Replace the usage of CONSOLE_T_DRVDATA with CONSOLE_T_BASE to fix this. Change-Id: I6d2ab0bc2c845c71f98b9dd64d89eef3252f4591 Reported-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 25 Feb, 2020 1 commit
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I058f793e4024fa7291e432f5be374a77faf16f36 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 12 Feb, 2020 1 commit
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Jacky Bai authored
Each memory region slot occupies 16bypte space, so correct the the offset of config register address. Change-Id: Ief8f21bb8ada78b5663768ee1e40f9e0eae57165 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 28 Jan, 2020 1 commit
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Madhukar Pappireddy authored
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I8b19e833a4e1067e1cfcc9bfaede7854e0e63004
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- 09 Jan, 2020 1 commit
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Madhukar Pappireddy authored
In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 04 Dec, 2019 2 commits
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Samuel Holland authored
This is not conforming C and does not compile with -fno-common. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I6535954cc567d6efa06919069b91e3f50975b073
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Samuel Holland authored
This was found by compiling with -fno-common: ./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed'; ./build/picopi/release/bl2/imx_caam.o:(.bss.__packed+0x0): first defined here __packed was intended to be the attribute macro from cdefs.h, not an object of the structure type. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Id02fac3f098be2d71c35c6b4a18012515532f32a
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- 06 Nov, 2019 1 commit
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Jacky Bai authored
Normally, SGI6 & SGI7 is used by non-secure world, these two SGIs should not be reserved for secure interrupt purpose. On i.MX8M platform, SGI8 is used for secure group0 IPI for DDR DVFS, So update the code to reserve SGI8 for secure world. Change-Id: Ib1ed9786e0a79bb729b120a0d4d791d13b6f048a Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 05 Nov, 2019 1 commit
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Jacky Bai authored
Add the basic support for opteed SPD on imx8mq & imx8mm. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I6c4855c89dea78d13d172c3d86cf047f829e51ce
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- 01 Aug, 2019 1 commit
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Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 24 Jul, 2019 1 commit
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Jacky Bai authored
Add the basic support for RDC init/config driver, this module driver can be enhanced more if necessary. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I290dc378d0d85671435f9de46d5aa790b4e006c8
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- 17 Jul, 2019 2 commits
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Jun Nie authored
The PicoPi iMX7D is a 2 board development board consisting of a System-on-Module and a carrier baseboard and optimized for the Internet-of-Things (IoT). This patch add basic support to this board. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: I009d85819c4f73b7063aab73d0f6ee74e6ef3fc4
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Jun Nie authored
For the iMX7 SOCs, part of the code for platform setup implementation can be reused and made common for all these SoCs. This patch extracts the common part for reuse. Signed-off-by: Jun Nie <jun.nie@linaro.org> Change-Id: I42fd4167e6903416df96a0159a046abf3896e878
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- 12 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ia0a10b4a30e63c0cbf1d0f8dfe5768e0a93ae1c7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 04 Jul, 2019 1 commit
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Jacky Bai authored
CAAM module must be initialized in secure world before it can be used in non-secure world. Change-Id: I042893667ddef99d8b6fc3902847d516d8591996 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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