- 21 May, 2021 1 commit
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Igor Opaniuk authored
In iMX8MM it is possible to have two copies of bootloader in SD/eMMC and switch between them. The switch is triggered either by the BootROM in case the bootloader image is faulty OR can be enforced by the user. To trigger that switch the PERSIST_SECONDARY_BOOT bit should be set in GPR10 SRC register. As the bit is retained after WARM reset, that permits to control BootROM behavior regarding what boot image it will boot after reset: primary or secondary. This is useful for reliable bootloader A/B updates, as it permits switching between two copies of bootloader at different offsets of the same storage. If the PERSIST_SECONDARY_BOOT is 0, the boot ROM uses address 0x8400 for the primary image. If the PERSIST_SECONDARY_BOOT is 1, the boot ROM reads that secondary image table from address 0x8200 on the boot media and uses the address specified in the table for the secondary image. Secondary Image Table contains the sector of secondary bootloader image, exluding the offset to that image (explained below in the note). To generate the Secondary Image Table, use e.g.: $ printf '\x0\x0\x0\x0\x0\x0\x0\x0\x33\x22\x11' '\x00\x00\x10\x0\x0\x00\x0\x0\x0' > /tmp/sit.bin $ hexdump -vC /tmp/sit.bin 00000000 00 00 00 00 00000004 00 00 00 00 00000008 33 22 11 00 <--- This is the "tag" 0000000c 00 10 00 00 <--- This is the "firstSectorNumber" 00000010 00 00 00 00 You can also use NXP script from [1][2] imx-mkimage tool for SIT generation. Note that the firstSectorNumber is NOT the offset of the IVT, but an offset of the IVT decremented by Image Vector Table offset (Table 6-25. Image Vector Table Offset and Initial Load Region Size for iMX8MM/MQ), so for secondary SPL copy at offset 0x1042 sectors, firstSectorNumber must be 0x1000 (0x42 sectors * 512 = 0x8400 bytes offset). In order to test redundant boot board should be closed and SD/MMC manufacture mode disabled, as secondary boot is not supported in the SD/MMC manufacture mode, which can be disabled by blowing DISABLE_SDMMC_MFG (example for iMX8MM): > fuse prog -y 2 1 0x00800000 For additional details check i.MX 8M Mini Apllication Processor Reference Manual, 6.1.5.4.5 Redundant boot support for expansion device chapter. [1] https://source.codeaurora.org/external/imx/imx-mkimage/ [2] scripts/gen_sit.sh Change-Id: I0a5cea7295a4197f6c89183d74b4011cada52d4c Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
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- 26 Apr, 2021 1 commit
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Olivier Deprez authored
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- 22 Apr, 2021 7 commits
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Manish Pandey authored
* changes: plat/qemu: add cortex-a72 support to 'virt' platform plat/qemu: include gicv2.mk
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Manish Pandey authored
* changes: plat: send an sgi to communicate to linux plat: xilinx: Error management support
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Venkatesh Yadav Abbarapu authored
Upon recieving the interrupt send an SGI. The sgi number is communicated by linux. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Change-Id: Ib8f07ff7132ba5ac202b546914efb16d04820ed3 Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
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Shubhrajyoti Datta authored
Add support for the trapping the IPI in TF-A. Register handler for the irq no 62 which is the IPI interrupt. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Change-Id: I9c04fdae7be3dda6a34a9b196274c0b5fdf39223 Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
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Manish Pandey authored
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Madhukar Pappireddy authored
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Manish Pandey authored
* changes: plat: imx8mm: Add in BL2 with FIP plat: imx8mm: Enable Trusted Boot
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- 21 Apr, 2021 11 commits
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Mark Dykes authored
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bipin.ravi authored
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Manish Pandey authored
* changes: renesas: rzg: Add support to identify EK874 RZ/G2E board drivers: renesas: common: watchdog: Add support for RZ/G2E drivers: renesas: rzg: Add QoS support for RZ/G2E drivers: renesas: rzg: Add PFC support for RZ/G2E drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC drivers: renesas: rzg: Add QoS support for RZ/G2N drivers: renesas: rzg: Add PFC support for RZ/G2N drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC drivers: renesas: rzg: Add QoS support for RZ/G2H drivers: renesas: rzg: Add PFC support for RZ/G2H drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC drivers: renesas: rzg: Switch using common ddr code drivers: renesas: ddr: Move to common
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Manish Pandey authored
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Alexei Fedorov authored
The Arm Generic Timer specification mandates that the interrupt associated with each timer is low level triggered, see: Arm Cortex-A76 Core: "Each timer provides an active-LOW interrupt output to the SoC." Arm Cortex-A53 MPCore Processor: "It generates timer events as active-LOW interrupt outputs and event streams." The following files in fdts\ fvp-base-gicv3-psci-common.dtsi fvp-base-gicv3-psci-aarch32-common.dtsi fvp-base-gicv2-psci-aarch32.dts fvp-base-gicv2-psci.dts fvp-foundation-gicv2-psci.dts fvp-foundation-gicv3-psci.dts describe interrupt types as edge rising IRQ_TYPE_EDGE_RISING = 0x01: interrupts = <1 13 0xff01>, <1 14 0xff01>, <1 11 0xff01>, <1 10 0xff01>; , see include\dt-bindings\interrupt-controller\arm-gic.h: which causes Linux to generate the warnings below: arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low arch_timer: WARNING: Please fix your firmware This patch adds GIC_CPU_MASK_RAW macro definition to include\dt-bindings\interrupt-controller\arm-gic.h, modifies interrupt type to IRQ_TYPE_LEVEL_LOW and makes use of type definitions in arm-gic.h. Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Manish Pandey authored
* changes: plat: xilinx: versal: Add the IPI CRC checksum macro support plat: xilinx: common: Rename the IPI CRC checksum macro
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Joanna Farley authored
* changes: build(hooks): add commitlint hook build(hooks): add Commitizen hook build(hooks): add Gerrit hook build(hooks): add Husky configuration
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Rajan Vaja authored
Counter frequency for generic timer of Arm-A53 based Application Processing Unit(APU) is not configuring in case if First Stage Boot Loader(FSBL) does not initialize counter frequency. This happens when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU). Because of that generic timer driver functionality is not working. So configure counter frequency during initialization. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
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Venkatesh Yadav Abbarapu authored
Add support for CRC checksum for IPI data when the macro IPI_CRC_CHECK is enabled. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I3c25c715885759076055c6505471339b5d6edcd5
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Venkatesh Yadav Abbarapu authored
Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and move the related defines to the common include. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I6d30b081ac607572a0b23e10ca8031bc90489e58
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Olivier Deprez authored
* changes: spmd: add FFA_INTERRUPT forwarding doc: spm: update messaging method field
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- 20 Apr, 2021 20 commits
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johpow01 authored
ELP processors can sometimes have different MIDR values or features so we are adding the "_arm" suffix to differentiate the reference implementation from other future versions. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20
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Manish Pandey authored
* changes: Add SiP service to configure Arm Ethos-N NPU plat/arm/juno: Add support to use hw_config in BL31
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Olivier Deprez authored
In the case of a SP pre-empted by a non-secure interrupt, the SPMC returns to the SPMD through the FFA_INTERRUPT ABI. It is then forwarded to the normal world driver hinting the SP has to be resumed after the non-secure interrupt has been serviced. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I51a694dddcb8ea30fa84e1f11d018bc2abec0a56
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Manish Pandey authored
As per FF-A v1.0 spec, Table 3.1, messaging method field also contains information about whether partition supports managed exit or not. Since a partition can support managed exit only if it supports direct messaging, so there are two new possible values, managed exit with only direct messaging or with both messaging methods. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ic77cfb37d70975c3a36c56f8b7348d385735f378
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Lad Prabhakar authored
Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Id7bdbc9b0d25aa9af496d58d4bd5055579edc104
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Lad Prabhakar authored
Add watchdog support for RZ/G2E SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ia813e051f6605028d0bb83967893ebd107fc8551
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Lad Prabhakar authored
Add QoS support for RZ/G2E SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I2c4373807ab8c550d86d6abc97f5b01f2fb78fb3
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Lad Prabhakar authored
Add pin control support for RZ/G2E SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I736724cc0dd32f2169018ed7f2f48319b039b61f
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Lad Prabhakar authored
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the same. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I454fb40af4f8ce6c4c0d2a53edb307326efd02df
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Lad Prabhakar authored
Add support to identify HopeRun HiHope RZ/G2N board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ib47aba84b63488247f6e9da1f5878140129766ce
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Lad Prabhakar authored
Select MMC_CH1 for eMMC on RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ib584b5203f38423ffe2ab52c6e6922f5b34a33ee
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Lad Prabhakar authored
Add QoS support for RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I663b50d9fb41b9b20a6b54795278659b2b184bc4
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Lad Prabhakar authored
Add pin control support for RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ib5eb4f3b1b75e158ec13c4eefdbe9688344206a3
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Lad Prabhakar authored
Add support for initializing DRAM on RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0
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Lad Prabhakar authored
Add support to identify HopeRun HiHope RZ/G2H board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I6b28350ef50595fea9a1b1b7353fcabaeb935970
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Lad Prabhakar authored
Select MMC_CH1 for eMMC on RZ/G2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I1bdfa462fd98b144042c014701b342b87e1efc9d
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Lad Prabhakar authored
Add QoS support for RZ/G2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: If7d8940148fc31887568fd501c6cab609e715ba4
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Lad Prabhakar authored
Add pin control support for RZ/G2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I06dc259d7d26a5a5313e8731ea72f846bfca09ed
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Lad Prabhakar authored
Add support for initializing DRAM on RZ/G2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9
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Lad Prabhakar authored
Switch using common ddr driver code from renesas/common/ddr directory for RZ/G2M SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I807dcb0bc5186bd32bc1c577945d28634bb10e1f
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