- 30 Oct, 2017 1 commit
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davidcunado-arm authored
Change the default option of ARM_TSP_RAM_LOCATION and Enlarge the BL2 size on ARM platforms
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- 27 Oct, 2017 1 commit
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davidcunado-arm authored
qemu/optee: load OP-TEE pageable part 2MB above OP-TEE image
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- 26 Oct, 2017 3 commits
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davidcunado-arm authored
qemu: fix holding pen mailbox sequence
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Etienne Carriere authored
OP-TEE dedicates the end of the Qemu secure DRAM as specific out-of-TEE secure RAM. To support this configuration the trusted firmware should not load OP-TEE resources in this area. To overcome the issue, OP-TEE pageable image is now loaded 2MByte above the secure RAM base address. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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davidcunado-arm authored
qemu: Add support for Trusted Board Boot
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- 25 Oct, 2017 3 commits
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Michalis Pappas authored
This patch adds support for TBB to qemu. An RSA ROT keypair is generated at build time and is included into BL1/BL2. The key and content certificates are read over semihosting. Fixes ARM-software/tf-issues#526 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
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Qixiang Xu authored
For Trusted Board Boot, BL2 needs more space to support the ECDSA and ECDSA+RSA algorithms. Change-Id: Ie7eda9a1315ce836dbc6d18d6588f8d17891a92d Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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Qixiang Xu authored
On Arm standard platforms, it runs out of SRAM space when TBB is enabled, so the TSP default location is changed to dram when TBB is enabled. Change-Id: I516687013ad436ef454d2055d4e6fce06e467044 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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- 24 Oct, 2017 1 commit
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Etienne Carriere authored
Before this change, plat_secondary_cold_boot_setup reads wake up mailbox as a byte array but through 64bit accesses on unaligned 64bit addresses. In the other hand qemu_pwr_domain_on wakes secondary cores by writing into a 64bit array. This change forces the 64bit mailbox format as PLAT_QEMU_HOLD_ENTRY_SIZE explicitly specifies it. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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- 23 Oct, 2017 4 commits
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davidcunado-arm authored
Fix edmac
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davidcunado-arm authored
Publish and Subscribe framework
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Jeenu Viswambharan authored
This allows other EL3 components to subscribe to CPU on events. Update Firmware Design guide to list psci_cpu_on_finish as an available event. Change-Id: Ida774afe0f9cdce4021933fcc33a9527ba7aaae2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
This light-weight framework enables some EL3 components to publish events which other EL3 components can subscribe to. Publisher can optionally pass opaque data for subscribers. The order in which subscribers are called is not defined. Firmware design updated. Change-Id: I24a3a70b2b1dedcb1f73cf48313818aebf75ebb6 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 21 Oct, 2017 3 commits
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davidcunado-arm authored
Migrate upstream platforms to using interrupt properties
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davidcunado-arm authored
New GIC APIs and specifying interrupt propertes
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davidcunado-arm authored
fiptool: Enable Visual Studio build
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- 20 Oct, 2017 1 commit
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davidcunado-arm authored
Add APIs to get and modify attributes of memory regions
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- 19 Oct, 2017 1 commit
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davidcunado-arm authored
uniphier: fix section of ROTPK hash
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- 18 Oct, 2017 6 commits
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davidcunado-arm authored
Update Foundation, AEM and Cortex Models versions
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davidcunado-arm authored
Fix use of MSR (immediate)
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Eleanor Bonnici authored
Trusted Firmware has been tested as part of its CI system against Cortex and Foundation models in the 11.1 Model release available on developer.arm.com. Trusted Firmware has also been tested against the v8.7 AEM model. This patch updates the user guide documentation to reflect the version of the Foundation, AEM and Cortex Models that Trusted Firmware has been tested against. Change-Id: Ia0f51469032427b6056567d151bf8144a7cf0e42 Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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Masahiro Yamada authored
This is not executable code. It should be put into .rodata instead of .text section. This produces more correct BL1 image when SEPARATE_CODE_AND_RODATA is defined. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Haojian Zhuang authored
Make RTC out of reset mode since it may be used in UEFI. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Init EDMA controller with non secure mode. A lot of peripherals are depend on EDMA controller. But EDMA controller is in secure mode by default. And this operation has to be executed in secure mode. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 17 Oct, 2017 11 commits
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davidcunado-arm authored
docs: Update Trusted Board Boot Requirements document number
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Jeenu Viswambharan authored
Change-Id: Ia8503d446cc8b4246013046f6294fea364c9c882 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
Change-Id: I1463a4f9b74d74d59ac1d37b7b9c8e53416ab904 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
Change-Id: Ibca6ea29be32783de666e0e0a0481668fc11860f Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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davidcunado-arm authored
Init and save / restore of PMCR_EL0 / PMCR
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davidcunado-arm authored
Update PSCI to v1.1
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Evan Lloyd authored
Updates are required to enable the fiptool utility to be built on a Windows platform. This change modifies the source files to enable building with Visual Studio (detected via preprocessor settings). The primary changes are: 1. Provide an implementation of the getopt_long function. This does not exist in the Visual Studio CRT libraries because Windows commands normally use '/' not '-' as an option indicator. 2. Redirect some function names to match those supported by the Visual Studio libraries (when building with Visual Studio). 2. Modify a structure name (stat) to match that provided by the Visual Studio libraries (_stat). Note - this change does not provide makefile updates. It only modifies the sources to enable the fiptool to be built from a Visual Studio project. In normal use the presence of FIPTOOL.EXE is enough to satisfy the make requirements. A makefile change may be derived from the Visual Studio command line information at some point in the future. Change-Id: I3ade77ea140246af3c030920b3f97c070087f111 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
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Antonio Nino Diaz authored
The implementation is the same as those used to disable it in EL3. Change-Id: Ibfe7e69034a691fbf57477c5a76a8cdca28f6b26 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Sandrine Bailleux authored
This patch introduces a new API in the translation tables library (v2), that allows to change the memory attributes of a memory region. It may be used to change its execution permissions and data access permissions. As a prerequisite, the memory must be already mapped. Moreover, it must be mapped at the finest granularity (currently 4 KB). Change-Id: I242a8c6f0f3ef2b0a81a61e28706540462faca3c Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Sandrine Bailleux authored
This patch introduces a new API in the translation tables library (v2), that allows to query the memory attributes of a memory block or a memory page. Change-Id: I45a8b39a53da39e7617cbac4bff5658dc1b20a11 Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Previously, in AArch32, `IMAGE_XLAT_DEFAULT_REGIME` wasn't defined. The translation regime is only used in the AArch64 port of the translation tables library v2, so this is not a problem for now, but future patches will use it. `IMAGE_EL` isn't used in AArch32, so it isn't needed to define it. Change-Id: I4acdb01a58658956ab94bd82ed5b7fee1aa6ba90 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 16 Oct, 2017 5 commits
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Jeenu Viswambharan authored
The GIC driver initialization currently allows an array of interrupts to be configured as secure. Future use cases would require more interrupt configuration other than just security, such as priority. This patch introduces a new interrupt property array as part of both GICv2 and GICv3 driver data. The platform can populate the array with interrupt numbers and respective properties. The corresponding driver initialization iterates through the array, and applies interrupt configuration as required. This capability, and the current way of supplying array (or arrays, in case of GICv3) of secure interrupts, are however mutually exclusive. Henceforth, the platform should supply either: - A list of interrupts to be mapped as secure (the current way). Platforms that do this will continue working as they were. With this patch, this scheme is deprecated. - A list of interrupt properties (properties include interrupt group). Individual interrupt properties are specified via. descriptors of type 'interrupt_prop_desc_t', which can be populated with the macro INTR_PROP_DESC(). A run time assert checks that the platform doesn't specify both. Henceforth the old scheme of providing list of secure interrupts is deprecated. When built with ERROR_DEPRECATED=1, GIC drivers will require that the interrupt properties are supplied instead of an array of secure interrupts. Add a section to firmware design about configuring secure interrupts. Fixes ARM-software/tf-issues#262 Change-Id: I8eec29e72eb69dbb6bce77879febf32c95376942 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
Change-Id: I795ec540942130b5ddc0fa1fd7167f7e1d1ae967 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
The helpers perform read-modify-write on GIC*_ICFGR registers, but don't serialise callers. Any serialisation must be taken care of by the callers. Change-Id: I71995f82ff2c7f70d37af0ede30d6ee18682fd3f Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
An earlier patch added provision for the platform to provide secure interrupt properties. ARM platforms already has a list of interrupts that fall into different secure groups. This patch defines macros that enumerate interrupt properties in the same fashion, and points the driver driver data to a list of interrupt properties rather than list of secure interrupts on ARM platforms. The deprecated interrupt list definitions are however retained to support legacy builds. Configuration applied to individual interrupts remain unchanged, so no runtime behaviour change expected. NOTE: Platforms that use the arm/common function plat_arm_gic_driver_init() must replace their PLAT_ARM_G1S_IRQS and PLAT_ARM_G0_IRQS macro definitions with PLAT_ARM_G1S_IRQ_PROPS and PLAT_ARM_G0_IRQ_PROPS macros respectively, using the provided INTR_PROP_DESC macro. Change-Id: I24d643b83e3333753a3ba97d4b6fb71e16bb0952 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
API documentation updated. Change-Id: I40feec1fe67a960d035061b54dd55610bc34ce1d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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