Commits · aebd4dc8ff81b39dd91f897c6871902b5d8aa677 · adam.huang / Arm Trusted Firmware

23 Apr, 2021 11 commits

mediatek: mt8195: Add gpio driver · aebd4dc8

mtk20895 authored Mar 31, 2021



Add gpio driver.
Signed-off-by: mtk20895 <zhiqiang.ma@mediatek.com>
Change-Id: I6ff6875c35294f56f2d8298d75cd18c230aad211

aebd4dc8

mediatek: mt8195: Add SiP service · 938fd425

Yidi Lin authored Mar 29, 2021



Add the basic SiP service

Change-Id: I21fe9d85eac4be9101b12c4b6c28294c5b93cb5f
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>

938fd425

mediatek: mt8195: Add CPU hotplug and MCDI support · fe985428

James Liao authored Jun 16, 2020



Implement PSCI platform OPs to support CPU hotplug and MCDI.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: I1321f7989c8a3d116d698768a7146e8f180ee9c0

fe985428

mediatek: mt8195: Add MCDI drivers · acc85548

James Liao authored Jun 15, 2020



Add MCDI related drivers to handle CPU powered on/off in CPU suspend.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: I6a6f9bf5d1d8bda1ee603d8bf3fc206437de7ad8

acc85548

mediatek: mt8195: Add SPMC driver · 0d82eff6

James Liao authored Jun 16, 2020



Add SPMC driver for CPU power on/off.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: If47d7f3f3b9965f3c0402ea6cdb917ad1d16bb32

0d82eff6

mediatek: mt8195: Initialize delay_timer · 65f0dd13

Yidi Lin authored Mar 26, 2021



Initialize delay_timer for delay functions.

Change-Id: Ib554135151f8b5c642b5a6511c942bb9efc0a47f
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>

65f0dd13

mediatek: mt8195: initialize systimer · 91550777

Yidi Lin authored Apr 22, 2021



Change-Id: I7e0fbd04b0cdf5da92b8ef39737342f2d66f5f10
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>

91550777

mediatek: mt8192: move timer driver to common folder · 46946036

Yidi Lin authored Mar 26, 2021



The timer driver can be shared with mt8195. Move the the timer
driver to common/.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I84c97ab9cc9b469f35e0f44dd8e7b2b95f1b3926

46946036

mediatek: mt8195: add sys_cirq support · e5490f95

gtk_pangao authored Mar 25, 2021



MT8192 cirq driver can be shared with MT8195. Move cirq driver to common
common folder.
Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com>
Change-Id: Iba5cdcfd2116f0bd07e0497250f2da45613e3a4f

e5490f95

mediatek: mt8195: initialize GIC · c63f1451

christine.zhu authored Mar 24, 2021



MT8192 GIC driver can be shared with MT8195. Move GIC driver to common
and do the initialization.
Signed-off-by: christine.zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I63f3e668b5ca6df8bcf17b5cd4d53fa84f330fed

c63f1451

Initialize platform for MediaTek MT8195 · 174a1cfe

Yidi Lin authored Mar 19, 2021



- Add basic platform setup
- Add MT8195 documentation at docs/plat/
- Add generic CPU helper functions
- Add basic register address

Change-Id: I7978e2f32e58900e5cf93f741ee8eaf8b8e3b842
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>

174a1cfe

21 Apr, 2021 10 commits

Merge "Add documentation for SMMUv3 driver in Hafnium(SPM)" into integration · 1d1e5006
Mark Dykes authored Apr 21, 2021

1d1e5006
Merge "Add "_arm" suffix to Makalu ELP CPU lib" into integration · dfe64665
bipin.ravi authored Apr 21, 2021

dfe64665

Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration · e9cd36f5

Manish Pandey authored Apr 21, 2021

* changes:
  renesas: rzg: Add support to identify EK874 RZ/G2E board
  drivers: renesas: common: watchdog: Add support for RZ/G2E
  drivers: renesas: rzg: Add QoS support for RZ/G2E
  drivers: renesas: rzg: Add PFC support for RZ/G2E
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
  renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
  drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
  drivers: renesas: rzg: Add QoS support for RZ/G2N
  drivers: renesas: rzg: Add PFC support for RZ/G2N
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
  renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
  drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC
  drivers: renesas: rzg: Add QoS support for RZ/G2H
  drivers: renesas: rzg: Add PFC support for RZ/G2H
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
  drivers: renesas: rzg: Switch using common ddr code
  drivers: renesas: ddr: Move to common

e9cd36f5

Merge "plat: xilinx: zynqmp: Configure counter frequency during initialization" into integration · d8dc8c9e
Manish Pandey authored Apr 21, 2021

d8dc8c9e

Merge changes I3c25c715,I6d30b081 into integration · 617632bf

Manish Pandey authored Apr 21, 2021

* changes:
  plat: xilinx: versal: Add the IPI CRC checksum macro support
  plat: xilinx: common: Rename the IPI CRC checksum macro

617632bf

Merge changes from topic "ck/conventional-commits" into integration · 745df305

Joanna Farley authored Apr 21, 2021

* changes:
  build(hooks): add commitlint hook
  build(hooks): add Commitizen hook
  build(hooks): add Gerrit hook
  build(hooks): add Husky configuration

745df305

plat: xilinx: zynqmp: Configure counter frequency during initialization · 9f0ddae3

Rajan Vaja authored Mar 26, 2021



Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stage Boot
Loader(FSBL) does not initialize counter frequency. This happens
when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU).
Because of that generic timer driver functionality is not working.
So configure counter frequency during initialization.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896

9f0ddae3

plat: xilinx: versal: Add the IPI CRC checksum macro support · 654bd99d

Venkatesh Yadav Abbarapu authored Feb 19, 2021



Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I3c25c715885759076055c6505471339b5d6edcd5

654bd99d

plat: xilinx: common: Rename the IPI CRC checksum macro · d7758354

Venkatesh Yadav Abbarapu authored Feb 19, 2021



Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and
move the related defines to the common include.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I6d30b081ac607572a0b23e10ca8031bc90489e58

d7758354

Merge changes from topic "od/ns-interrupts" into integration · 89a05821
Olivier Deprez authored Apr 21, 2021
```
* changes:
  spmd: add FFA_INTERRUPT forwarding
  doc: spm: update messaging method field
```
89a05821

20 Apr, 2021 19 commits

Add "_arm" suffix to Makalu ELP CPU lib · 97bc7f0d

johpow01 authored Apr 20, 2021



ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from other future versions.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20

97bc7f0d

Merge changes from topic "arm_ethosn_npu_sip" into integration · 207ef629
Manish Pandey authored Apr 20, 2021
```
* changes:
  Add SiP service to configure Arm Ethos-N NPU
  plat/arm/juno: Add support to use hw_config in BL31
```
207ef629

spmd: add FFA_INTERRUPT forwarding · 386dc365

Olivier Deprez authored Apr 02, 2021



In the case of a SP pre-empted by a non-secure interrupt, the SPMC
returns to the SPMD through the FFA_INTERRUPT ABI. It is then forwarded
to the normal world driver hinting the SP has to be resumed after the
non-secure interrupt has been serviced.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I51a694dddcb8ea30fa84e1f11d018bc2abec0a56

386dc365

doc: spm: update messaging method field · 2480e4c3

Manish Pandey authored Sep 25, 2020

As per FF-A v1.0 spec, Table 3.1, messaging method field also contains
information about whether partition supports managed exit or not.
Since a partition can support managed exit only if it supports direct
messaging, so there are two new possible values, managed exit with only
direct messaging or with both messaging methods.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic77cfb37d70975c3a36c56f8b7348d385735f378

2480e4c3

renesas: rzg: Add support to identify EK874 RZ/G2E board · bcf43f04

Lad Prabhakar authored Mar 19, 2021



Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id7bdbc9b0d25aa9af496d58d4bd5055579edc104

bcf43f04

drivers: renesas: common: watchdog: Add support for RZ/G2E · 2c10d4e2

Lad Prabhakar authored Mar 19, 2021



Add watchdog support for RZ/G2E SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ia813e051f6605028d0bb83967893ebd107fc8551

2c10d4e2

drivers: renesas: rzg: Add QoS support for RZ/G2E · 05cc21de

Lad Prabhakar authored Dec 21, 2020



Add QoS support for RZ/G2E SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I2c4373807ab8c550d86d6abc97f5b01f2fb78fb3

05cc21de

drivers: renesas: rzg: Add PFC support for RZ/G2E · 5bfea97e

Lad Prabhakar authored Dec 29, 2020



Add pin control support for RZ/G2E SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I736724cc0dd32f2169018ed7f2f48319b039b61f

5bfea97e

drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC · 30663f34

Lad Prabhakar authored Mar 19, 2021



DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the
same.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I454fb40af4f8ce6c4c0d2a53edb307326efd02df

30663f34

renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board · a4d86f67

Lad Prabhakar authored Mar 19, 2021



Add support to identify HopeRun HiHope RZ/G2N board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib47aba84b63488247f6e9da1f5878140129766ce

a4d86f67

drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC · bf007a56

Lad Prabhakar authored Mar 18, 2021



Select MMC_CH1 for eMMC on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib584b5203f38423ffe2ab52c6e6922f5b34a33ee

bf007a56

drivers: renesas: rzg: Add QoS support for RZ/G2N · f8ecfd68

Lad Prabhakar authored Mar 18, 2021



Add QoS support for RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I663b50d9fb41b9b20a6b54795278659b2b184bc4

f8ecfd68

drivers: renesas: rzg: Add PFC support for RZ/G2N · 744c5664

Lad Prabhakar authored Dec 29, 2020



Add pin control support for RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib5eb4f3b1b75e158ec13c4eefdbe9688344206a3

744c5664

drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC · b939cbbb

Lad Prabhakar authored Apr 19, 2021



Add support for initializing DRAM on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0

b939cbbb

renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board · ec3e2f67

Lad Prabhakar authored Dec 21, 2020



Add support to identify HopeRun HiHope RZ/G2H board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I6b28350ef50595fea9a1b1b7353fcabaeb935970

ec3e2f67

drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC · 4a6f4d2e

Lad Prabhakar authored Dec 21, 2020



Select MMC_CH1 for eMMC on RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I1bdfa462fd98b144042c014701b342b87e1efc9d

4a6f4d2e

drivers: renesas: rzg: Add QoS support for RZ/G2H · 86c3cc30

Lad Prabhakar authored Dec 11, 2020



Add QoS support for RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: If7d8940148fc31887568fd501c6cab609e715ba4

86c3cc30

drivers: renesas: rzg: Add PFC support for RZ/G2H · a51d7062

Lad Prabhakar authored Mar 18, 2021



Add pin control support for RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I06dc259d7d26a5a5313e8731ea72f846bfca09ed

a51d7062

drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC · fe5929c1

Lad Prabhakar authored Apr 19, 2021



Add support for initializing DRAM on RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9

fe5929c1