Skip to content

GitLab

Switch branch/tag
  1. 28 Sep, 2018 25 commits
  3. 27 Sep, 2018 1 commit
    • Shawn Guo's avatar
      poplar: fix build error with POPLAR_RECOVERY=1 · d5ed2946
      Shawn Guo authored 
      Commit eba1b6b3

 ("plat/poplar: migrate to mmc framework") defines
variable 'info' without !POPLAR_RECOVERY protection, and hence causes
the following unused variable error with POPLAR_RECOVERY=1 build.

plat/hisilicon/poplar/bl1_plat_setup.c: In function ‘bl1_platform_setup’:
plat/hisilicon/poplar/bl1_plat_setup.c:95:25: error: unused variable ‘info’ [-Werror=unused-variable]
  struct mmc_device_info info;
                         ^~~~

The patches fixes the build error with POPLAR_RECOVERY=1.
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
      d5ed2946
  5. 24 Sep, 2018 1 commit
  7. 19 Sep, 2018 1 commit
    • Andre Przywara's avatar
      drivers: i2c: mentor: move platform code into header files · dfc0fb27
      Andre Przywara authored 
      

At the moment we have two I2C stub drivers (for the Allwinner and the
Marvell platform), which #include the actual .c driver file.
Change this into the more usual design, by renaming and moving the stub
drivers into platform specific header files and including these from the
actual driver file. The platform specific include directories make sure
the driver picks up the right header automatically.
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      dfc0fb27
  9. 18 Sep, 2018 1 commit
  11. 17 Sep, 2018 2 commits
    • Andre Przywara's avatar
      allwinner: sun50i_h6: initialise I2C just before powering down · 159c5249
      Andre Przywara authored 
      

Even though we initialise the platform part and the I2C controller
itself at boot time, we actually only access the bus on power down.
Meanwhile a rich OS might have configured the I2C pins differently or
even disabled the controller.
So repeat the platform setup and controller initialisation just before
we actually access the bus to power off the system. This is safe,
because at this point the rich OS should no longer be running.
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      159c5249
    • Andre Przywara's avatar
      allwinner: sun50i_h6: improve I2C setup · 1a910bce
      Andre Przywara authored 
      

Drop the unnecessary check for the I2C pins being already configured as
I2C pins (we actually don't care).
Also avoid resetting *every* peripheral that is covered by the PRCM reset
controller, instead just clear the one line connected to the I2C controller.
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      1a910bce
  13. 10 Sep, 2018 1 commit
  15. 09 Sep, 2018 1 commit
  17. 07 Sep, 2018 7 commits
    • Icenowy Zheng's avatar
      allwinner: implement system power down on H6 w/ AXP805 · 5069c1cf
      Icenowy Zheng authored 
      

The AXP805 PMIC used with H6 is capable of shutting down the system.

Add support for using it to shut down the system power.

The original placeholder power off code is moved to A64 code, as it's
still TODO to implement PMIC operations for A64.
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
      5069c1cf
    • Icenowy Zheng's avatar
      allwinner: sun50i_h6: add initial AXP805 PMIC code · 6d372828
      Icenowy Zheng authored 
      

The OTT reference design of Allwinner H6 SoC uses an X-Powers AXP805
PMIC.

Add initial code for it.

Currently it's only detected.
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
      6d372828
    • Icenowy Zheng's avatar
      allwinner: call PMIC setup code · 7c26b6ec
      Icenowy Zheng authored 
      

As the ATF may need to do some power initialization on Allwinner
platform with AXP PMICs, call the PMIC setup code in BL31.

Stub of PMIC setup code is added, to prevent undefined reference.
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
      7c26b6ec
    • Sathees Balya's avatar
      juno: Revert FWU update detect mechanism · 4da6f6cd
      Sathees Balya authored 
      The patch 7b56928a

 unified the FWU mechanism on FVP and Juno
platforms due to issues with MCC firmware not preserving the
NVFLAGS. With MCCv150 firmware, this issue is resolved. Also
writing to the NOR flash while executing from the same flash
in Bypass mode had some stability issues. Hence, since the
MCC firmware issue is resolved, this patch reverts to the
NVFLAGS mechanism to detect FWU. Also, with the introduction
of SDS (Shared Data Structure) by the SCP, the reset syndrome
needs to queried from the appropriate SDS field.

Change-Id: If9c08f1afaaa4fcf197f3186887068103855f554
Signed-off-by: default avatarSathees Balya <sathees.balya@arm.com>
Signed-off-by: default avatarSoby Mathew <Soby.Mathew@arm.com>
      4da6f6cd
    • Alexei Fedorov's avatar
      ARM Platforms:Enable non-secure access to UART1 · 2431d00f
      Alexei Fedorov authored 
      

Adds an undocumented build option that enables non-secure access to
the PL011 UART1.
This allows a custom build where the UART can be used as a serial debug
port for WinDbg (or other debugger) connection.

This option is not documented in the user guide, as it is provided as a
convenience for Windows debugging, and not intended for general use.
In particular, enabling non-secure access to the UART might allow
a denial of service attack!

Change-Id: I4cd7d59c2cac897cc654ab5e1188ff031114ed3c
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: default avatarEvan Lloyd <evan.lloyd@arm.com>
      2431d00f
    • John Tsichritzis's avatar
      Add cache flush after BL1 writes heap info to DTB · 63cc2658
      John Tsichritzis authored 
      

A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we
ensure that the heap info written to the DTB always gets written back to
memory.  Hence, sharing this info with other images is guaranteed.

Change-Id: I0faada31fe7a83854cd5e2cf277ba519e3f050d5
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      63cc2658
    • John Tsichritzis's avatar
      Additional runtime check for DTB presence in BL2 · a606031e
      John Tsichritzis authored 
      

In Mbed TLS shared heap code, an additional sanity check is introduced
in BL2. Currently, when BL2 shares heap with BL1, it expects the heap
info to be found in the DTB. If for any reason the DTB is missing, BL2
cannot have the heap address and, hence, Mbed TLS cannot proceed. So,
BL2 cannot continue executing and it will eventually crash.  With this
change we ensure that if the DTB is missing BL2 will panic() instead of
having an unpredictable crash.

Change-Id: I3045ae43e54b7fe53f23e7c2d4d00e3477b6a446
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      a606031e