- 26 Apr, 2021 2 commits
-
-
Manish Pandey authored
This will help in keeping source file generic and conditional compilation can be contained in platform provided dt files. Signed-off-by:Manish Pandey <manish.pandey2@arm.com> Change-Id: I3c6e0a429073f0afb412b9ba521ce43f880b57fe
-
Olivier Deprez authored
-
- 22 Apr, 2021 7 commits
-
-
Manish Pandey authored
* changes: plat/qemu: add cortex-a72 support to 'virt' platform plat/qemu: include gicv2.mk
-
Manish Pandey authored
* changes: plat: send an sgi to communicate to linux plat: xilinx: Error management support
-
Venkatesh Yadav Abbarapu authored
Upon recieving the interrupt send an SGI. The sgi number is communicated by linux. Signed-off-by:
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Change-Id: Ib8f07ff7132ba5ac202b546914efb16d04820ed3 Signed-off-by:
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
-
Shubhrajyoti Datta authored
Add support for the trapping the IPI in TF-A. Register handler for the irq no 62 which is the IPI interrupt. Signed-off-by:
-
Manish Pandey authored
-
Madhukar Pappireddy authored
-
Manish Pandey authored
* changes: plat: imx8mm: Add in BL2 with FIP plat: imx8mm: Enable Trusted Boot
-
- 21 Apr, 2021 11 commits
-
-
Mark Dykes authored
-
bipin.ravi authored
-
Manish Pandey authored
* changes: renesas: rzg: Add support to identify EK874 RZ/G2E board drivers: renesas: common: watchdog: Add support for RZ/G2E drivers: renesas: rzg: Add QoS support for RZ/G2E drivers: renesas: rzg: Add PFC support for RZ/G2E drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC drivers: renesas: rzg: Add QoS support for RZ/G2N drivers: renesas: rzg: Add PFC support for RZ/G2N drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC drivers: renesas: rzg: Add QoS support for RZ/G2H drivers: renesas: rzg: Add PFC support for RZ/G2H drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC drivers: renesas: rzg: Switch using common ddr code drivers: renesas: ddr: Move to common
-
Manish Pandey authored
-
Alexei Fedorov authored
The Arm Generic Timer specification mandates that the interrupt associated with each timer is low level triggered, see: Arm Cortex-A76 Core: "Each timer provides an active-LOW interrupt output to the SoC." Arm Cortex-A53 MPCore Processor: "It generates timer events as active-LOW interrupt outputs and event streams." The following files in fdts\ fvp-base-gicv3-psci-common.dtsi fvp-base-gicv3-psci-aarch32-common.dtsi fvp-base-gicv2-psci-aarch32.dts fvp-base-gicv2-psci.dts fvp-foundation-gicv2-psci.dts fvp-foundation-gicv3-psci.dts describe interrupt types as edge rising IRQ_TYPE_EDGE_RISING = 0x01: interrupts = <1 13 0xff01>, <1 14 0xff01>, <1 11 0xff01>, <1 10 0xff01>; , see include\dt-bindings\interrupt-controller\arm-gic.h: which causes Linux to generate the warnings below: arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low arch_timer: WARNING: Please fix your firmware This patch adds GIC_CPU_MASK_RAW macro definition to include\dt-bindings\interrupt-controller\arm-gic.h, modifies interrupt type to IRQ_TYPE_LEVEL_LOW and makes use of type definitions in arm-gic.h. Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9 Signed-off-by:Alexei Fedorov <Alexei.Fedorov@arm.com>
-
Manish Pandey authored
* changes: plat: xilinx: versal: Add the IPI CRC checksum macro support plat: xilinx: common: Rename the IPI CRC checksum macro
-
Joanna Farley authored
* changes: build(hooks): add commitlint hook build(hooks): add Commitizen hook build(hooks): add Gerrit hook build(hooks): add Husky configuration
-
Rajan Vaja authored
Counter frequency for generic timer of Arm-A53 based Application Processing Unit(APU) is not configuring in case if First Stage Boot Loader(FSBL) does not initialize counter frequency. This happens when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU). Because of that generic timer driver functionality is not working. So configure counter frequency during initialization. Signed-off-by:Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
-
Venkatesh Yadav Abbarapu authored
Add support for CRC checksum for IPI data when the macro IPI_CRC_CHECK is enabled. Signed-off-by: -
Venkatesh Yadav Abbarapu authored
Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and move the related defines to the common include. Signed-off-by: -
Olivier Deprez authored
* changes: spmd: add FFA_INTERRUPT forwarding doc: spm: update messaging method field
-
- 20 Apr, 2021 20 commits
-
-
johpow01 authored
ELP processors can sometimes have different MIDR values or features so we are adding the "_arm" suffix to differentiate the reference implementation from other future versions. Signed-off-by:John Powell <john.powell@arm.com> Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20
-
Manish Pandey authored
* changes: Add SiP service to configure Arm Ethos-N NPU plat/arm/juno: Add support to use hw_config in BL31
-
Olivier Deprez authored
In the case of a SP pre-empted by a non-secure interrupt, the SPMC returns to the SPMD through the FFA_INTERRUPT ABI. It is then forwarded to the normal world driver hinting the SP has to be resumed after the non-secure interrupt has been serviced. Signed-off-by:Olivier Deprez <olivier.deprez@arm.com> Change-Id: I51a694dddcb8ea30fa84e1f11d018bc2abec0a56
-
Manish Pandey authored
As per FF-A v1.0 spec, Table 3.1, messaging method field also contains information about whether partition supports managed exit or not. Since a partition can support managed exit only if it supports direct messaging, so there are two new possible values, managed exit with only direct messaging or with both messaging methods. Signed-off-by: -
Lad Prabhakar authored
Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874). Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Id7bdbc9b0d25aa9af496d58d4bd5055579edc104
-
Lad Prabhakar authored
Add watchdog support for RZ/G2E SoC. Signed-off-by:
-
Lad Prabhakar authored
Add QoS support for RZ/G2E SoC. Signed-off-by:
-
Lad Prabhakar authored
Add pin control support for RZ/G2E SoC. Signed-off-by:
-
Lad Prabhakar authored
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the same. Signed-off-by:
-
Lad Prabhakar authored
Add support to identify HopeRun HiHope RZ/G2N board. Signed-off-by:
-
Lad Prabhakar authored
Select MMC_CH1 for eMMC on RZ/G2N SoC. Signed-off-by:
-
Lad Prabhakar authored
Add QoS support for RZ/G2N SoC. Signed-off-by:
-
Lad Prabhakar authored
Add pin control support for RZ/G2N SoC. Signed-off-by:
-
Lad Prabhakar authored
Add support for initializing DRAM on RZ/G2N SoC. Signed-off-by:
-
Lad Prabhakar authored
Add support to identify HopeRun HiHope RZ/G2H board. Signed-off-by:
-
Lad Prabhakar authored
Select MMC_CH1 for eMMC on RZ/G2H SoC. Signed-off-by:
-
Lad Prabhakar authored
Add QoS support for RZ/G2H SoC. Signed-off-by:
-
Lad Prabhakar authored
Add pin control support for RZ/G2H SoC. Signed-off-by:
-
Lad Prabhakar authored
Add support for initializing DRAM on RZ/G2H SoC. Signed-off-by:
-
Lad Prabhakar authored
Switch using common ddr driver code from renesas/common/ddr directory for RZ/G2M SoC. Signed-off-by:
-
