- 23 Jun, 2021 1 commit
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Patrick Georgi authored
To quote jwerner in T925: "The __sramdata in the declaration is a mistake, the correct target section for that global needs to be .pmusram.data. This used to be in .sram.data once upon a time but then the suspend.c stuff got added and required it to be moved to PMUSRAM. I guess they forgot to update that part in the declaration and since the old GCC seemed to silently prefer the attribute in the definition, nobody noticed." This fixes building with gcc 11. fix #T925 Change-Id: I2b91542277c95cf487eaa1344927294d5d1b8f2b Signed-off-by: Patrick Georgi <pgeorgi@google.com>
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- 17 Dec, 2019 1 commit
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Heiko Stuebner authored
The calls to secure ddr regions on rk3288 and rk3399 use parameters of base and size - as it custom for specifying memory regions, but the functions themself expect start and endpoints of the area. This only works by chance for the TZRAM, as it starts a 0x0 and therefore its end location is the same as its size. To not fall into a trap later on adapt the functions to really take base+size parameters. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: Idb9fab38aa081f3335a4eca971e7b7f6757fbbab
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- 13 Dec, 2019 1 commit
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Joshua Watt authored
Instead of stringizing the paths to binary files, add them as string defines on the command line (e.g. -DFOO=\"BAR\" instead of -DFOO=BAR). This prevents macros from being expanded inside the string value itself. For example, -DFOO=/path/with-linux-in-it would have been expanded to "/path/with-1-in-it" because `linux=1` is one of the standard GCC defines. Change-Id: I7b65df3c9930faed4f1aff75ad726982ae3671e6 Signed-off-by: Joshua Watt <JPEWhacker@gmail.com>
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- 10 Dec, 2019 1 commit
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Piotr Szczepanik authored
This patch fixes hangs that happen after soft resetting of rk3399. Signed-off-by: Piotr Szczepanik <piter75@gmail.com> Change-Id: If41b12ba1dfcb2ba937361b58eafd50bf5c483d4
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- 19 Nov, 2019 1 commit
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Justin Chadwell authored
Variable shadowing is, according to the C standard, permitted and valid behaviour. However, allowing a local variable to take the same name as a global one can cause confusion and can make refactoring and bug hunting more difficult. This patch moves -Wshadow from WARNING2 into the general warning group so it is always used. It also fixes all warnings that this introduces by simply renaming the local variable to a new name Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 09 Aug, 2019 1 commit
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Heiko Stuebner authored
The rk3399 suspend code saves and restores the debug uart settings, but right now always does this for the default uart. Right now this works only by chance for the majority of rk3399 boards, which do not deviate from that default. But both Coreboot as well as U-Boot-based platforms can actually use different uarts for their output, which can be configured from either devicetree or Coreboot-variables. To fix this, just use the stored uart-base information instead of the default constant. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I1ea059d59a1126f6f8702315df7e620e632b686e
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- 24 Jul, 2019 1 commit
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Julius Werner authored
This patch changes all Rockchip platforms to use the new common BL aux parameter helpers. Since the parameter space is now cleanly split in generic and vendor-specific parameters and the COREBOOT_TABLE parameter is now generic, the parameter type number for that parameter has to change. Since it only affects coreboot which always builds TF as a submodule and includes its headers directly to get these constants, this should not cause any issues. In general, after this point, we should avoid changing already assigned parameter type numbers whenever possible. Change-Id: Ic99ddd1e91ff5e5fe212fa30c793a0b8394c9dad Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 11 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ib7fc54e4141cc4f1952a18241bc18671b36e2168 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 24 Apr, 2019 1 commit
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Christoph Müllner authored
GCC complains for quite some versions, when compiling the M0 firmware for Rockchip's rk3399 platform, about an invalid type of function 'main': warning: return type of 'main' is not 'int' [-Wmain] This patch addresses this, by renaming the function to 'm0_main'. Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: I10887f2bda6bdb48c5017044c264139004f7c785
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 08 Nov, 2018 1 commit
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 21 Sep, 2018 1 commit
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Daniel Boulby authored
Ensure case clauses: * Terminate with an unconditional break, return or goto statement. * Use conditional break, return or goto statements as long as the end of the case clause is unreachable; such case clauses must terminate with assert(0) /* Unreachable */ or an unconditional __dead2 function call * Only fallthough when doing otherwise would result in less readable/maintainable code; such case clauses must terminate with a /* Fallthrough */ comment to make it clear this is the case and indicate that a fallthrough is intended. This reduces the chance of bugs appearing due to unintended flow through a switch statement Change-Id: I70fc2d1f4fd679042397dec12fd1982976646168 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 22 Aug, 2018 1 commit
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Antonio Nino Diaz authored
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 11 Jul, 2018 1 commit
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Roberto Vargas authored
These directives are only used when stabs debugging information is used, but we use ELF which uses DWARF debugging information. Clang assembler doesn't support these directives, and removing them makes the code more compatible with clang. Change-Id: I2803f22ebd24c0fe248e04ef1b17de9cec5f89c4 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 13 Jun, 2018 1 commit
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Paul Kocialkowski authored
The stdint header was introduced to rk3399's plat_sip_calls.c in order to fix missing stdint definitions. However, ordering headers alphabetically caused the fix to be ineffective, as stint was then included after the offending header file (dfs.h). Move the stdint include to that header to properly fix the issue. Change-Id: Ieaad37a7932786971488ab58fc5b169bfa79e197 Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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- 15 May, 2018 3 commits
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Derek Basehore authored
To catch early hangs in resume, this sets up the watchdog before anything else in the pmusram code (ignoring setting up the stack...). This uses hard coded settings for the watchdog until the proper watchdog restore later on in the firmware/kernel. This also restores the old watchdog register values before the PLLs are restored to make sure we don't temporarily switch over to a 1/3s timeout on the watchdog when the pclk_wdt goes from 4MHz to 100MHz. Change-Id: I8f7652089a88783271b17482117b4609330abe80 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Lin Huang authored
All the m0 code run in SRAM before, but we need to watch PMU_POWER_ST when SOC enter into FSM, and SRAM will shutdown during this time, so this code need run in PMUSRAM. But PMUSRAM only 8K space, we can not put all the m0 binary into PMUSRAM, Split the M0 binary into two, dram part still run in SRAM, and suspend part run in PMUSRAM. Change-Id: Ie08bdf3e2b8838f12b9297fe60ab0aad219684b1 Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
we need to enable PMU_WKUP_RST_EN for pmu powermode configure, since enable wakeup reset will hold the soc status, so the SOC will not affect by some power or other single glitch when resume, and keep the soc in the right status. And it not need to enable DDRIO_RET_HW_DE_REQ, the ddr resume will do it manual. Change-Id: Ib4af897ffb3cb63dc2aa9a6002e5d9ef86ee4a49 Signed-off-by: Lin Huang <hl@rock-chips.com>
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- 07 Apr, 2018 1 commit
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Derek Basehore authored
This fixes an off by 576x bug the the sram_udelay code. The wrong value was multipled by the system ticks per mhz value (which is 24), so we delayed for 1/576th of the requested time. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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- 26 Mar, 2018 1 commit
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Jonathan Wright authored
Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7. Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
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- 21 Mar, 2018 1 commit
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Antonio Nino Diaz authored
When the source code says 'SMCC' it is talking about the SMC Calling Convention. The correct acronym is SMCCC. This affects a few definitions and file names. Some files have been renamed (smcc.h, smcc_helpers.h and smcc_macros.S) but the old files have been kept for compatibility, they include the new ones with an ERROR_DEPRECATED guard. Change-Id: I78f94052a502436fdd97ca32c0fe86bd58173f2f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 20 Mar, 2018 1 commit
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Lin Huang authored
there are two fix for save/restore watchdog register: 1. watchdog plck will shutdown after secure_watchdog_disable(), so need to save register before it and restore after secure_watchdog_enable(). 2. need write 0x76 to cnt_restart to keep watchdog alive when restore watchdog register. Change-Id: I1f6fbceae22186e3b72a87df6332a110adf37479 Signed-off-by: Lin Huang <hl@rock-chips.com>
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- 30 Jan, 2018 1 commit
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Caesar Wang authored
Coverity scan done for the coreboot project found the issue: Coverity (*** CID 1385418: Memory - illegal accesses (OVERRUN)) Coverity (*** CID 1385419: Memory - corruptions (OVERRUN)) Fix the Converity error issue with store_cru[] loop needs to be one element bigger. Fixes: ARM-software/tf-issues#544 Change-Id: I420f0a660b24baaa5fc5e78fca242cf750c9bbc7 Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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- 24 Jan, 2018 4 commits
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Derek Basehore authored
This adds calls to the GICv3 save/restore functions for the GIC distributor and redistributor. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
We were looping for MAX_WAIT_COUNT in several places without any delays, so this adds the delays to make those loops more predictable. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
The code was accidentally restoring the QOS on suspend and saving the QOS on resume. This is the opposite of what we want. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
This brings ATF into line with the kernel on the timeout for power domains turning on. We could actually timeout (when we shouldn't) on resume when turning power domains on. The guaranteed maximum delay is now 10ms. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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- 29 Aug, 2017 7 commits
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Lin Huang authored
when shutdown logic power rail, the some sgrf register value will reset, so need to reinitilize secure. Change-Id: I8ad0570432e54441fe1c60dd2960a81fd58f7163 Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
we will use timer in pmusarm, when logic power rail shutdown, the secure timer will gone, so need to initial it in pmusram. Change-Id: I472e7eec3fc197f56223e6fff9167556c1c5e3bc Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
we do not have enough pmusram space now, so use slice1 to restore ddr slice1 ~ slice4, that's will save more pmusram space. Change-Id: Id54a7944f33d01a8f244cee6a8a0707bfe4d42da Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
Change-Id: Ia59adf48cf14eb627721264765bce50cb31065ef Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
pd_alive control cru, grf, timer, gpio and wdt, when turn off logic power rail, these register value will back to reset value, we need to save them value in suspend and restore them when resuem, since timer will reinitial in kernel, so it not need to save/restore. Change-Id: I0fc2a011d3cdc04b66ffbf728e769eb28b51ee38 Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
when logic power rail shutdown, CRU register will back to reset value, ddr use abpll as clock source when do suspend, we need to save and dpll value in pmusram, then set back these ddr clock back to dpll when dddr resume. Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
when shutdown logic power rail, the uart register value will reset, so need to reinitilize debug uart. Change-Id: I48d3535c0068fd671dea6ea32e908612992faf62 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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- 14 Jul, 2017 1 commit
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Isla Mitchell authored
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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- 05 Jul, 2017 1 commit
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Ziyuan Xu authored
Decrypt device private keys which transfer from kernel, then stuff it to DP controller. So that DP driver could start HDCP authentication in kernel. Change-Id: If3c2cd99bca811fe5fc30acc88bf5dc1afd7416d Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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- 30 Jun, 2017 1 commit
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Caesar Wang authored
This patch fixes the two things as follows: 1) rk3399_flash_l2_b" seems to be a typo. That's "flush", not "flash". 2) fixes the warnings log. We always hit the warnings thing during the suspend, as below log: .. [ 51.022334] CPU5: shutdown [ 51.025069] psci: CPU5 killed. INFO: sdram_params->ddr_freq = 928000000 WARNING: rk3399_flash_l2_b:reg 28830380,wait When the L2 completes the clean and invalidate sequence, it asserts the L2FLUSHDONE signal. The SoC can now deassert L2FLUSHREQ signal and then the L2 deasserts L2FLUSHDONE. Then, a loop without a delay isn't really great to measure time. We should probably add a udelay(10) or so in there and then maybe replace the WARN() after the loop. In the actual tests, the L2 cache will take ~4ms by default for big cluster. In the real world that give 10ms for the enough margin, like the ddr/cpu/cci frequency and other factors that will affect it. Change-Id: I55788c897be232bf72e8c7b0e10cf9b06f7aa50d Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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- 26 Jun, 2017 1 commit
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Ziyuan Xu authored
For some reason, HDCP key decrytion can't open source in ATF, so we build it as hdcp.bin. Besides declare the handler for decrypting. Change-Id: Ia67ff2442ab43cb3ee4875b3d59cc1608e854b4b Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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- 08 Jun, 2017 2 commits
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Lin Huang authored
with PMU_PERILP_PD_EN bit enable, the soc will shutdown cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con, spi, i2c, uart, saradc, tsadc when suspend, we have M0 code need to run when suspend in normal SRAM, so we need to take care of that. Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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Derek Basehore authored
This moves the DRAM restore code to PMUSRAM. This is so that the voltage domain that contains the SRAM that it was stored in before may be turned off during system suspend. Change-Id: Id761181a30caadd12f1ce061d1034f3159a76d28 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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