- 27 Apr, 2021 2 commits
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Aditya Angadi authored
Add board support for RD-N2 Cfg1 variant of RD-N2 platform. It is a variant of RD-N2 platform with a reduced interconnect mesh size (3x3) and core count (8-cores). Its platform variant id is 1. Change-Id: I34ad35c5a5c1e9b69a658fb92ed00e5bc5fe72f3 Signed-off-by:Aditya Angadi <aditya.angadi@arm.com>
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Aditya Angadi authored
A Neoverse reference design platform can have two or more variants that differ in core count, cluster count or other peripherals. To allow reuse of platform code across all the variants of a platform, introduce build option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design platforms. The range of allowed values for the build option is platform specific. The recommended range is an interval of non negative integers. An example usage of the build option is make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1 Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359 Signed-off-by:
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- 26 Apr, 2021 1 commit
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Manish Pandey authored
This will help in keeping source file generic and conditional compilation can be contained in platform provided dt files. Signed-off-by:Manish Pandey <manish.pandey2@arm.com> Change-Id: I3c6e0a429073f0afb412b9ba521ce43f880b57fe
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- 23 Apr, 2021 15 commits
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Manish Pandey authored
sgm775 is an old platform and is no longer maintained by Arm and its fast model FVP_CSS_SGM-775 is no longer available for download. This platform is now superseded by Total Compute(tc) platforms. This platform is now deprecated but the source will be kept for cooling off period of 2 release cycle before removing it completely. Signed-off-by: -
Yidi Lin authored
mt8195 also uses mt6359p RTC. Revice mt8192 RTC and share the driver with mt8195. Change-Id: I20c73f6e0af67ef9d4c3d4e0ff373f93950e07db Signed-off-by:Yidi Lin <yidi.lin@mediatek.com>
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Yidi Lin authored
mt8195 also uses PMIC mt6359p. The only difference is the pwrap register definition. Change-Id: I9962263c46187d1344f14f857bf4b51e33aedda0 Signed-off-by: -
Yidi Lin authored
Add system_reset function in PSCI ops Signed-off-by: -
mtk20895 authored
Add gpio driver. Signed-off-by:mtk20895 <zhiqiang.ma@mediatek.com> Change-Id: I6ff6875c35294f56f2d8298d75cd18c230aad211
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Yidi Lin authored
Add the basic SiP service Change-Id: I21fe9d85eac4be9101b12c4b6c28294c5b93cb5f Signed-off-by: -
James Liao authored
Implement PSCI platform OPs to support CPU hotplug and MCDI. Signed-off-by:James Liao <jamesjj.liao@mediatek.com> Change-Id: I1321f7989c8a3d116d698768a7146e8f180ee9c0
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James Liao authored
Add MCDI related drivers to handle CPU powered on/off in CPU suspend. Signed-off-by: -
James Liao authored
Add SPMC driver for CPU power on/off. Signed-off-by: -
Yidi Lin authored
Initialize delay_timer for delay functions. Change-Id: Ib554135151f8b5c642b5a6511c942bb9efc0a47f Signed-off-by: -
Yidi Lin authored
Change-Id: I7e0fbd04b0cdf5da92b8ef39737342f2d66f5f10 Signed-off-by: -
Yidi Lin authored
The timer driver can be shared with mt8195. Move the the timer driver to common/. Signed-off-by: -
gtk_pangao authored
MT8192 cirq driver can be shared with MT8195. Move cirq driver to common common folder. Signed-off-by:gtk_pangao <gtk_pangao@mediatek.com> Change-Id: Iba5cdcfd2116f0bd07e0497250f2da45613e3a4f
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christine.zhu authored
MT8192 GIC driver can be shared with MT8195. Move GIC driver to common and do the initialization. Signed-off-by:christine.zhu <christine.zhu@mediatek.corp-partner.google.com> Change-Id: I63f3e668b5ca6df8bcf17b5cd4d53fa84f330fed
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Yidi Lin authored
- Add basic platform setup - Add MT8195 documentation at docs/plat/ - Add generic CPU helper functions - Add basic register address Change-Id: I7978e2f32e58900e5cf93f741ee8eaf8b8e3b842 Signed-off-by:
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- 22 Apr, 2021 2 commits
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Venkatesh Yadav Abbarapu authored
Upon recieving the interrupt send an SGI. The sgi number is communicated by linux. Signed-off-by:
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Change-Id: Ib8f07ff7132ba5ac202b546914efb16d04820ed3 Signed-off-by:
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
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Shubhrajyoti Datta authored
Add support for the trapping the IPI in TF-A. Register handler for the irq no 62 which is the IPI interrupt. Signed-off-by:
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- 21 Apr, 2021 3 commits
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Rajan Vaja authored
Counter frequency for generic timer of Arm-A53 based Application Processing Unit(APU) is not configuring in case if First Stage Boot Loader(FSBL) does not initialize counter frequency. This happens when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU). Because of that generic timer driver functionality is not working. So configure counter frequency during initialization. Signed-off-by:Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
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Venkatesh Yadav Abbarapu authored
Add support for CRC checksum for IPI data when the macro IPI_CRC_CHECK is enabled. Signed-off-by: -
Venkatesh Yadav Abbarapu authored
Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and move the related defines to the common include. Signed-off-by:
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- 20 Apr, 2021 17 commits
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johpow01 authored
ELP processors can sometimes have different MIDR values or features so we are adding the "_arm" suffix to differentiate the reference implementation from other future versions. Signed-off-by:John Powell <john.powell@arm.com> Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20
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Lad Prabhakar authored
Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874). Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Id7bdbc9b0d25aa9af496d58d4bd5055579edc104
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Lad Prabhakar authored
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the same. Signed-off-by:
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Lad Prabhakar authored
Add support to identify HopeRun HiHope RZ/G2N board. Signed-off-by:
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Lad Prabhakar authored
Add support for initializing DRAM on RZ/G2N SoC. Signed-off-by:
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Lad Prabhakar authored
Add support to identify HopeRun HiHope RZ/G2H board. Signed-off-by:
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Lad Prabhakar authored
Add support for initializing DRAM on RZ/G2H SoC. Signed-off-by:
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Lad Prabhakar authored
Switch using common ddr driver code from renesas/common/ddr directory for RZ/G2M SoC. Signed-off-by:
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Lad Prabhakar authored
Move ddr driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Mikael Olsson authored
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode the non-secure world cannot access the registers needed to use the NPU. To still allow the non-secure world to use the NPU, a SiP service has been added that can delegate non-secure access to the registers needed to use it. Only the HW_CONFIG for the Arm Juno platform has been updated to include the device tree for the NPU and the platform currently only loads the HW_CONFIG in AArch64 builds. Signed-off-by:Mikael Olsson <mikael.olsson@arm.com> Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
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Mikael Olsson authored
To make it possible to use the hw_config device tree for dynamic configuration in BL31 on the Arm Juno platform. A placeholder hw_config has been added that is included in the FIP and a Juno specific BL31 setup has been added to populate fconf with the hw_config. Juno's BL2 setup has been updated to align it with the new behavior implemented in the Arm FVP platform, where fw_config is passed in arg1 to BL31 instead of soc_fw_config. The BL31 setup is expected to use the fw_config passed in arg1 to find the hw_config. Signed-off-by: -
Konstantin Porotchkin authored
Subversion is not reflecting the Marvell sources variant anymore. This patch removes version.mk from Marvell plafroms. Signed-off-by:Konstantin Porotchkin <kostap@marvell.com> Change-Id: I8f3afbe3fab3a38da68876f77455f449f5fe0179
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Konstantin Porotchkin authored
Move efuse definitions to a separate header file for later usage with other FW modules. Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f Signed-off-by:
sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by:
Yi Guo <yi.guo@cavium.com>
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Konstantin Porotchkin authored
Use single 64b register for the return value instead of two 32b. Report an error if caller requested larger than than 64b random number in a single SMC call. Signed-off-by:
Nadav Haklai <nadavh@marvell.com>
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Alex Evraev authored
This patch forces rx training on 10G ports as part of comphy_smc call from Linux. Signed-off-by:
Alex Evraev <alexev@marvell.com> Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763 Tested-by:
Stefan Chulski <stefanc@marvell.com> Reviewed-by:
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Konstantin Porotchkin authored
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations. Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by:
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Guo Yi authored
Fixed a bug that the actually bit number was used as a mask to select LD0 or LD1 fuse Signed-off-by:
Guo Yi <yguo@cavium.com> Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146 Tested-by:
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