- 21 Apr, 2021 8 commits
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Manish Pandey authored
* changes: renesas: rzg: Add support to identify EK874 RZ/G2E board drivers: renesas: common: watchdog: Add support for RZ/G2E drivers: renesas: rzg: Add QoS support for RZ/G2E drivers: renesas: rzg: Add PFC support for RZ/G2E drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC drivers: renesas: rzg: Add QoS support for RZ/G2N drivers: renesas: rzg: Add PFC support for RZ/G2N drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC drivers: renesas: rzg: Add QoS support for RZ/G2H drivers: renesas: rzg: Add PFC support for RZ/G2H drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC drivers: renesas: rzg: Switch using common ddr code drivers: renesas: ddr: Move to common
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Manish Pandey authored
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Manish Pandey authored
* changes: plat: xilinx: versal: Add the IPI CRC checksum macro support plat: xilinx: common: Rename the IPI CRC checksum macro
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Joanna Farley authored
* changes: build(hooks): add commitlint hook build(hooks): add Commitizen hook build(hooks): add Gerrit hook build(hooks): add Husky configuration
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Rajan Vaja authored
Counter frequency for generic timer of Arm-A53 based Application Processing Unit(APU) is not configuring in case if First Stage Boot Loader(FSBL) does not initialize counter frequency. This happens when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU). Because of that generic timer driver functionality is not working. So configure counter frequency during initialization. Signed-off-by:Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
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Venkatesh Yadav Abbarapu authored
Add support for CRC checksum for IPI data when the macro IPI_CRC_CHECK is enabled. Signed-off-by:Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I3c25c715885759076055c6505471339b5d6edcd5
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Venkatesh Yadav Abbarapu authored
Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and move the related defines to the common include. Signed-off-by: -
Olivier Deprez authored
* changes: spmd: add FFA_INTERRUPT forwarding doc: spm: update messaging method field
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- 20 Apr, 2021 32 commits
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Manish Pandey authored
* changes: Add SiP service to configure Arm Ethos-N NPU plat/arm/juno: Add support to use hw_config in BL31
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Olivier Deprez authored
In the case of a SP pre-empted by a non-secure interrupt, the SPMC returns to the SPMD through the FFA_INTERRUPT ABI. It is then forwarded to the normal world driver hinting the SP has to be resumed after the non-secure interrupt has been serviced. Signed-off-by:Olivier Deprez <olivier.deprez@arm.com> Change-Id: I51a694dddcb8ea30fa84e1f11d018bc2abec0a56
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Manish Pandey authored
As per FF-A v1.0 spec, Table 3.1, messaging method field also contains information about whether partition supports managed exit or not. Since a partition can support managed exit only if it supports direct messaging, so there are two new possible values, managed exit with only direct messaging or with both messaging methods. Signed-off-by:Manish Pandey <manish.pandey2@arm.com> Change-Id: Ic77cfb37d70975c3a36c56f8b7348d385735f378
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Lad Prabhakar authored
Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874). Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Id7bdbc9b0d25aa9af496d58d4bd5055579edc104
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Lad Prabhakar authored
Add watchdog support for RZ/G2E SoC. Signed-off-by:
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Lad Prabhakar authored
Add QoS support for RZ/G2E SoC. Signed-off-by:
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Lad Prabhakar authored
Add pin control support for RZ/G2E SoC. Signed-off-by:
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Lad Prabhakar authored
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the same. Signed-off-by:
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Lad Prabhakar authored
Add support to identify HopeRun HiHope RZ/G2N board. Signed-off-by:
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Lad Prabhakar authored
Select MMC_CH1 for eMMC on RZ/G2N SoC. Signed-off-by:
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Lad Prabhakar authored
Add QoS support for RZ/G2N SoC. Signed-off-by:
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Lad Prabhakar authored
Add pin control support for RZ/G2N SoC. Signed-off-by:
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Lad Prabhakar authored
Add support for initializing DRAM on RZ/G2N SoC. Signed-off-by:
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Lad Prabhakar authored
Add support to identify HopeRun HiHope RZ/G2H board. Signed-off-by:
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Lad Prabhakar authored
Select MMC_CH1 for eMMC on RZ/G2H SoC. Signed-off-by:
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Lad Prabhakar authored
Add QoS support for RZ/G2H SoC. Signed-off-by:
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Lad Prabhakar authored
Add pin control support for RZ/G2H SoC. Signed-off-by:
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Lad Prabhakar authored
Add support for initializing DRAM on RZ/G2H SoC. Signed-off-by:
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Lad Prabhakar authored
Switch using common ddr driver code from renesas/common/ddr directory for RZ/G2M SoC. Signed-off-by:
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Lad Prabhakar authored
Move ddr driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Madhukar Pappireddy authored
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Mikael Olsson authored
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode the non-secure world cannot access the registers needed to use the NPU. To still allow the non-secure world to use the NPU, a SiP service has been added that can delegate non-secure access to the registers needed to use it. Only the HW_CONFIG for the Arm Juno platform has been updated to include the device tree for the NPU and the platform currently only loads the HW_CONFIG in AArch64 builds. Signed-off-by:Mikael Olsson <mikael.olsson@arm.com> Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
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Mikael Olsson authored
To make it possible to use the hw_config device tree for dynamic configuration in BL31 on the Arm Juno platform. A placeholder hw_config has been added that is included in the FIP and a Juno specific BL31 setup has been added to populate fconf with the hw_config. Juno's BL2 setup has been updated to align it with the new behavior implemented in the Arm FVP platform, where fw_config is passed in arg1 to BL31 instead of soc_fw_config. The BL31 setup is expected to use the fw_config passed in arg1 to find the hw_config. Signed-off-by: -
Manish Pandey authored
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Manish Pandey authored
* changes: plat/marvell: remove subversion from Marvell make files drivers/marvell: check if TRNG unit is present plat/marvell: a8k: move efuse definitions to separate header plat/marvell/armada: fix TRNG return SMC handling drivers: marvell: comphy: add rx training on 10G port plat/marvell/armada: postpone MSS CPU startup to BL31 stage plat: marvell: armada: a8k: Fix LD selector mask plat/marvell/armada: allow builds without MSS support drivers: marvell: misc-dfx: extend dfx whitelist drivers: marvell: add support for secure read/write of dfx register-set ddr_phy: use smc calls to access ddr phy registers drivers: marvell: thermal: use dedicated function for thermal SiPs drivers: marvell: add thermal sensor driver and expose it via SIP service fix: plat: marvell: fix MSS loader for A8K family
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Konstantin Porotchkin authored
Subversion is not reflecting the Marvell sources variant anymore. This patch removes version.mk from Marvell plafroms. Signed-off-by:Konstantin Porotchkin <kostap@marvell.com> Change-Id: I8f3afbe3fab3a38da68876f77455f449f5fe0179
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Konstantin Porotchkin authored
Some Marvell SoCs may have crypto engine disabled in the HW. This patch checks the AP LD0 efuse for crypto engine/TRNG presence before initializing the driver. Change-Id: I441e7c69a137106bd36302b028b04c0b31896dbd Signed-off-by:
sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by:
Yi Guo <yi.guo@cavium.com>
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Konstantin Porotchkin authored
Move efuse definitions to a separate header file for later usage with other FW modules. Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f Signed-off-by:
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Konstantin Porotchkin authored
Use single 64b register for the return value instead of two 32b. Report an error if caller requested larger than than 64b random number in a single SMC call. Signed-off-by:
Nadav Haklai <nadavh@marvell.com>
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Alex Evraev authored
This patch forces rx training on 10G ports as part of comphy_smc call from Linux. Signed-off-by:
Alex Evraev <alexev@marvell.com> Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763 Tested-by:
Stefan Chulski <stefanc@marvell.com> Reviewed-by:
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Konstantin Porotchkin authored
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations. Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by:
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Guo Yi authored
Fixed a bug that the actually bit number was used as a mask to select LD0 or LD1 fuse Signed-off-by:
Guo Yi <yguo@cavium.com> Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146 Tested-by:
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