- 11 Dec, 2018 3 commits
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Antonio Nino Diaz authored
Change-Id: Ib7c2529b85bb5930d44907edfc8ead13d3b1ef4d Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
SPM needs to map a number of regions on behalf of the secure partition. Previously, it used to get a list of them from platform code using the plat_get_secure_partition_mmap() API. Now it gets them from the resource description structure. The SPM<->SP shared buffer is mapped dynamically at EL3. This buffer is used to pass information between SPM and SP, so it must be mapped at EL3 as well in order to be used by SPM. Dynamic translation tables have been enabled when the Trusted Firmware is compiled with SPM support. Change-Id: I64ad335e931661812a0a60558e60372e1e5e6b72 Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Load SP and RD from package instead of relying on RD being already loaded in memory and the SP being loaded as a BL32 image. Change-Id: I18d4fbf4597656c6a7e878e1d7c01a8a324f3f8a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 10 Dec, 2018 4 commits
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Antonio Nino Diaz authored
This information is retrieved from the resource description now. Change-Id: Iaae23945eb2c45305cdc6442853e42f4e04fe094 Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
This information is defined by the Secure Partition in the resource description. Change-Id: Ia7db90c5de8360a596106880d3f6a632a88d3ea8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Introduce helpers to create resource description struct, as well as code to load the information from DTB files. Change-Id: I0f5bb94eb8b01c6cb53fe807a9db0c05a70d7a43 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Iec265dc85d44f35048d1fbcfbe55960d45570027 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 07 Dec, 2018 3 commits
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Julius Werner authored
This patch makes the build system link the console framework code by default, like it already does with other common libraries (e.g. cache helpers). This should not make a difference in practice since TF is linked with --gc-sections, so the linker will garbage collect all functions and data that are not referenced by any other code. Thus, if a platform doesn't want to include console code for size reasons and doesn't make any references to console functions, the code will not be included in the final binary. To avoid compatibility issues with older platform ports, only make this change for the MULTI_CONSOLE_API. Change-Id: I153a9dbe680d57aadb860d1c829759ba701130d3 Signed-off-by: Julius Werner <jwerner@chromium.org>
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Julius Werner authored
Crash reporting via the default consoles registered by MULTI_CONSOLE_API has been broken since commit d35cc347 (Console: Use callee-saved registers), which was introduced to allow console drivers written in C. It's not really possible with the current crash reporting framework to support console drivers in C, however we should make sure that the existing assembly drivers that do support crash reporting continue to work through the MULTI_CONSOLE_API. This patch fixes the problem by creating custom console_putc() and console_flush() implementations for the crash reporting case that do not use the stack. Platforms that want to use this feature will have to link plat/common/aarch64/crash_console_helpers.S explicitly. Also update the documentation to better reflect the new reality (of this being an option rather than the expected default for most platforms). Change-Id: Id0c761e5e2fddaf25c277bc7b8ab603946ca73cb Signed-off-by: Julius Werner <jwerner@chromium.org>
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Julius Werner authored
Commit e74afb65 (Deprecate weak crash console functions) deprecated the default inclusion of weak definitions for plat_crash_console functions in plat/common/aarch64/platform_helpers.S. The code was later copied out to plat/common/aarch64/crash_console_helpers.S so platforms can link it explicitly if they want to. However, since deprecation does not mean removal, the same code is also still duplicated in platform_helpers.S. The duplicated code contains both empty stubs for the !MULTI_CONSOLE_API case, and a real implementation that used to work but was broken by commit d35cc347 (Console: Use callee-saved registers) for MULTI_CONSOLE_API. It's not great to have both of these duplicated in two files, so this patch splits them up: in platform_helpers.S we'll only keep the empty stubs (guarded by !ERROR_DEPRECATED), which should not regress functionality since the MULTI_CONSOLE_API implementation was already broken anyway. In crash_console_helpers.S, we'll only keep the MULTI_CONSOLE_API version, which is enough both as an implementation in itself and as a sample for how to reimplement these functions in a platform-specific file. Change-Id: I83d95a90ab6aac597dc2ea2f2797ac2c8ed075d4 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 06 Dec, 2018 12 commits
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Chandni Cherukuri authored
SGI-Clark.Helios platform is similar to SGI-Clark.Ares platform. The difference between these two platforms is the CPU type and the number of CPUs. Add the base support for SGI-Clark.Helios platform. Change-Id: I2b04cb3fb953907848b4fab016e3648899ca4256 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
For SGI-Clark.Helios platform, at present, only the CPU power ON/OFF ops are supported. So override the PSCI ops to allow callbacks only for CPU power ON/OFF operations. Change-Id: Idc0a3deb78cb850310cbe849d77604fa9881579c Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
SGI-Clark.Helios platform is based on multi-threaded CPUs and uses an additional thread power domain level as well. Define a power domain tree descriptor 'sgi_clark_helios_pd_tree_desc' for SGI-Clark.Helios platform and let the function 'plat_get_power_domain_tree_desc' pick up the correct power domain tree descriptor based on the platform. Change-Id: Ibc6d551b570bc740053316a3608c455679d9155b Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Marek Vasut authored
Generate a /reserved-memory node for FCNL in the DT passed to subsequent stages, so they will know how the FCNL is configured. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Generate /compatible string for the platform, so that the subsequent stages know which platform they are running on. This could be useful when ie. building U-Boot that contains DTs for multiple platforms and can thus decide on which platform it is running. This would ultimately allow single bootloader binary for all Gen3 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Pass DTB containing DRAM layout from BL2 to BL33 via register x3, so that the BL33 can simply consume it and get accurate DRAM layout info. BL33 is in most usecases U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Use array of start-size tuples for the DRAM banks and call single function which iterates over this array to report the DRAM info. This is in preparation for expanding this to generate FDT for the next stage. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Print the DRAM configuration only after the DRAM was initialized. This will be useful when deduplicating code populating FDT passed to U-Boot, since it will contain the same macros as bl2_advertise_dram_size(). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Make the DRAM configuration debug print consistent for all supported SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
There is nothing preventing H3 older than v3.0 from printing the DRAM configuration, just like v3.0 and newer. Drop the check and let all H3 revisions print DRAM configuration in BL2. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
RCAR_DRAM_DDR3L_MEMCONF = 2 means E3 with 1GBx4 memory configuration. Add debug print for this configuration for completeness sake. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Just move the DRAM layout information into separate function, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 05 Dec, 2018 2 commits
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Chandni Cherukuri authored
With the two new APIs 'plat_arm_sgi_get_platform_id' and 'plat_arm_sgi_get_config_id' that are available now, BL31 need not depend on hw_config device tree to identify the platform. In addition to this, the existing hardware description in hw_config can be limited to use by BL33 and not by the operating system. So the hardware description from hw_config dts can be moved into nt_fw_config dts and the use of hw_config dts can be removed. Change-Id: I873b7e1e72823d3ec5d253a848e85ae724f09e49 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Bai Ping authored
i.MX8MQ is new SOC of NXP's i.MX8M family based on A53. It can provide industry-leading audio, voice and video processing for applications that scale from consumer home audio to industrial building automation and mobile computers this patchset add the basic supoort to boot up the 4 X A53. more feature will be added later. Signed-off-by: Bai Ping <ping.bai@nxp.com>
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- 04 Dec, 2018 10 commits
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Konstantin Porotchkin authored
Sync the platform code version with current Marvell LSP. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Igal Liberman authored
Very rarely, during cpuidle operations the following error is seen: "PM MSG Trigger Timeout". This is caused by slow handling of message interrutps in the PM FW running on CM3 (under heavy PM operation load). This is not a real issue, so we extend the timeout to avoid the error prints. Change-Id: I92fd6f2ff1ddf208b216c123880ded28a00b6e0e Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59670 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
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Konstantin Porotchkin authored
Add static configuration for SFI+ 10Gbps interface on SERDES Lane 4. This is just a copy of Lane 2 static values, not optimized. Board-to-board iperf test shows up to 6Gbps transfer speed. Change-Id: I024d2ac132f7fa6c342a64367f3dca2123a27e97 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
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Christine Gharzuzi authored
- Number of open power switches for CPUs should be three and now two. - This patch updates the value of open power switches from 0xfd (two power-switches) to 0xfc (three power-switches). Change-Id: I2783ab7f04bbbb6da78eeedcabe4636f9a774512 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add support for SVC test builds for tuning AVS values. Update the SVC procedure and add EEPROM access. Add support for AP807 AVS values (10 bits wide). Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Christine Gharzuzi authored
- Update CPU frequency on AP807 to 2GHz for SAR 0x0. - Increase AVS to 0.88V for 2GHz clock Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Igal Liberman authored
In Armada 8K DB boards, PCIe initialization can be executed only once because PCIe reset performed during chip power on and it cannot be executed via GPIO later. This means that power on can be executed only once, when it's called from the bootloader. Power on: Read bit 21 of the mode, it marks if the caller is the bootloader or the Linux Kernel. Power off: Check if the comphy was already configured to PCIe, if yes, check if the caller is bootloader, if both conditions are true (PCIe mode and called by Linux) - skip the power-off. In addition, fix incorrect documentation describing mode fields - PCIe width is 3 bits, not 2. NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work with it). Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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Grzegorz Jaszczyk authored
Do not power off the CPU1 since there is no way to wake it up (wake-up is causing CPU0 reset as well duo to HW bug). Quote from errata Ref #13 [In power saving mode, both cores must be powered off]: "When Core 0 is on and Core 1 is in power-off state, a Core 1 wake-up resets Core 0 as well and puts Core 0 back to ROM". To overcome described HW bug instead of powering the CPU off, let it reach WFI instruction, which is invoked by generic psci_do_cpu_off function after platform handler finishes. This will put the core in low power state and give a chance to wake it up. Before this change, after running secondary kernel via kexec, only one core was up, now both cores are up. Change-Id: I87f144867550728055d9b8a2edb84a14539acab7 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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Peng Fan authored
Add tzc380 support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 03 Dec, 2018 1 commit
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Chandni Cherukuri authored
Add two new functions 'plat_arm_sgi_get_platform_id' and 'plat_arm_sgi_get_config_id' which will be implemented by all the SGI platforms. These functions can be used to determine the part number and configuration id of the SGI platforms. In BL2, these functions are used to populate the 'system-id' node. In BL31, these functions are used to populate the 'sgi_plat_info_t' structure with the part number and configuration id of the platform. Change-Id: I3bacda933527724a3b4074ad4ed5b53a81ea4689 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 29 Nov, 2018 2 commits
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Ryan Grachek authored
This is needed to utilize the DMA controller on the hikey960 Signed-off-by: Ryan Grachek <ryan@edited.us>
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Chandni Cherukuri authored
In order to allow Arm platforms to override the default list of PSCI callbacks, remove the existing weak implementation of 'plat_arm_psci_override_pm_ops' function and let all the Arm platforms implement their own 'plat_arm_psci_override_pm_ops' function. For platforms that support SCMI protocol, the function 'css_scmi_override_pm_ops' can be additionally used as well to override the default PSCI callbacks. Change-Id: If7c27468bd51a00ea9c2a3716b5894163f5a9f3c Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 27 Nov, 2018 3 commits
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Chandni Cherukuri authored
For platforms with multi-threaded CPUs, the number of power domains supported would be more than the value currently defined by PLAT_MAX_PWR_LVL. So move the PLAT_MAX_PWR_LVL macro to platform specific code and let the platform define the number of power domain levels. Change-Id: I21c0682e62b397860b2999031a0c9c5ce0d28eed Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
To support platforms which are based on multi-threaded CPUs, override the weak implementation of plat_arm_get_cpu_pe_count function to return the number of threads supported by the CPU used in the platform. Change-Id: Ia680773f1277b17e2d3d2414d87943dcece33e89 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the system power domain level can be different for CSS platforms that use multi-threaded CPUs. So, in preparation towards adding support for platforms that use multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the CSS platform. Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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