Remove the hard coding of all the MMU related registers with 0 and
disable MMU by clearing the M and C bit in SCTLR_ELx.

Also remove use of partially qualified asm helper functions.

Change-Id: I383083f93a0a53143e58f146faf7755198f6a6ca

Change-Id: I6d7c040d7569df601a12007dd2413c39f40f07ce

In the Juno port, this function returns the first entry of the
frequency modes table from the memory mapped generic timer.

Workaround for issue #68

On Juno, we don't need the following components so this patch
removes them of the images:
 - semihosting support;
 - FVP power controller support;
 - GICv3 support.

 - Distinguish Juno specific from platform agnostic constants
 - Define constants for Juno TZC-400 NSAID

It is easier to have all platform constants in the same place.

As for FVP platforms, Juno provides some LEDs that we can
use to report exceptions during the early boot code.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

Removing semihosting from the plat_io_storage code copied from FVP.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

Juno has a "taped out" BL1.

To run your own BL1 on the board, you have to place it in a "ROM bypass"
address and configure the platform to boot from there.

The agreed bypass address is an offset of 0x03EC0000 from the start of
NOR flash (0x08000000), which equates to 0x0BEC0000.

To run the model using a BL1 in bypass mode, you should use a parameter
set something like this:

	<path to>/FVP_CSS_Juno3 \
		-C css.aon.scp.ROMloader.fname=<SCP ROM filename> \
		--data css.cluster1.cpu0=bl1.bin@0x0BEC0000 \
		-C soc.scc.apps_alt_boot=0x0BEC0000

To build BL1 as a ROM located at address zero, you can over-ride the
default value for TZROM_BASE by passing parameters to make, eg:

	ASFLAGS="-D TZROM_BASE=0x00000000" \
	CFLAGS="-D TZROM_BASE=0x00000000" \
	CROSS_COMPILE=aarch64-linux-gnu- \
	make PLAT=juno DEBUG=1 all

Then you can launch the model using a command such as:

	<path to>/FVP_CSS_Juno3 \
		-C css.aon.scp.ROMloader.fname=<SCP ROM filename> \
		-C css.trustedBootROMloader.fname=<path to>/bl1.bin \
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

Currently UEFI and Linux are using SMC calls in the 'ARM Architecture'
Owning Entity range so lets implement these to get things working.

UEFI probably doesn't actually need to issue the ID_PRESENCE and ID_UID
calls it does, and the device-tree used by Linux could specify the PSCI
identifiers instead. After those changes, this patch isn't required.
Signed-off-by: Jon Medhurst <tixy@linaro.org>

This is a temporary solution for issue #20
Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

The SCP Ready command is sent by the SCP to indicate that the BL3-0 RAM
Firmware image is successfully up and running.
Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Note, on Juno mailboxes are 16 bytes because any bigger and they would
overlap the memory used for MHU payload data for SCP->AP transfers.
Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Juno doesn't have TZDRAM as FVP does, and there is real reason why we
need a special memory region for bl31_args anyway, assuming we take care
to copy it in BL31 before BL2's memory is reused.
Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>