- 20 Oct, 2018 4 commits
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Andre Przywara authored
The SRAM in the Allwinner H6 SoC starts at 0x2000, with the last part ending at 0x117fff (although with gaps in between). So SUNXI_SRAM_SIZE should be 0xf8000, not 0x98000. Fix this to map the arisc exception vector area, which we will need shortly. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
According to the documentation, platforms may choose to trade memory footprint for performance (and elegancy) by not providing a separately mapped coherent page. Since a debug build is getting close to the SRAM size limit already, this allows us to save about 3.5KB of BSS and have some room for future enhancements. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
At the moment we map as much of the DRAM into EL3 as possible, however we actually don't use it. The only exception is the secure DRAM for BL32 (if that is configured). To decrease the memory footprint of ATF, we save on some page tables by reducing the memory mapping to the actually required regions: SRAM, device MMIO, secure DRAM and U-Boot (to be used later). This introduces a non-identity mapping for the DRAM regions. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
For the two different platforms we support in the Allwinner port we mostly rely on header files covering the differences. This leads to the platform.mk files in the respective directories to be almost identical. To avoid further divergence and make sure that one platform doesn't break accidentally, let's create a shared allwinner-common.mk file and include that from the platform directory. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 18 Oct, 2018 6 commits
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Soby Mathew authored
Add MMC support for STM32MP1
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Soby Mathew authored
rcar_gen3: initial support
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Soby Mathew authored
Allow D-Cache to remain on during core power-down
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Soby Mathew authored
Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled
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Soby Mathew authored
plat/arm: relocate the jump_if_cpu_midr macro.
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Soby Mathew authored
plat/arm: Small reorganization of platform code
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- 17 Oct, 2018 17 commits
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
- ddr - pfc [pin function controller] - qos [bandwidth] checkpatch.pl is generating too many errors.
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Jorge Ramirez-Ortiz authored
Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
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- 16 Oct, 2018 2 commits
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Andrew F. Davis authored
Leave the caches on and explicitly flush any data that may be stale when the core is powered down. This prevents non-coherent interconnect access which has negative side- effects on AM65x. Signed-off-by: Andrew F. Davis <afd@ti.com>
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Roberto Vargas authored
When HW_ASSISTED_COHERENCY is enabled we can use spinlocks instead of using the more complex and slower bakery algorithm. Change-Id: I9d791a70050d599241169b9160a67e57d5506564 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 15 Oct, 2018 6 commits
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Deepak Pandey authored
macro jump_if_cpu_midr is used commonly by many arm platform. It has now been relocated to common place to remove duplication of code. Change-Id: Ic0876097dbc085df4f90eadb4b7687dde7c726da Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Whereas the GPT table is read with io_block, the binaries to be loaded (e.g. BL33) cannot use it, as it is not suitable to read them block by block, or the boot time would be very bad. Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
This IO is required to read binaries with STM32 header. This header is added with the stm32image tool. Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
To boot on eMMC or SD-cards, STM32MP1 platform needs: - GPT_IMAGE_ID to read GPT table on those devices - STM32_IMAGE_ID and IO_TYPE_STM32IMAGE to read images with STM32 header - IO_TYPE_MMC to have a IO for MMC devices Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
This driver is for the STMicroelectronics sdmmc2 IP which is in STM32MP1 SoC. It uses the MMC framework, and can address either eMMC or SD-card. Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 12 Oct, 2018 5 commits
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Dimitris Papastamos authored
drivers: partition: correct compilation error in VERBOSE mode
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Dimitris Papastamos authored
Introduce object pool allocator
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Dimitris Papastamos authored
pl011: cnds: cbmem: 16550: Fix comments
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Antonio Nino Diaz authored
The comments with the prototypes of the register functions of the console drivers are incorrect. The arguments are wrong. This patch fixes them. Change-Id: I38c4b481ee69e840780111c42f03c0752eb6315c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Soby Mathew authored
Makefile: Support totally quiet output with -s
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